[llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

[Stuart Hastings]

Author: stuart
Date: Wed Jun  1 13:32:25 2011
New Revision: 132411

URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev
Log:
Fix double FGETSIGN to work on x86_32; followup to 132396.
rdar://problem/5660695

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun  1 13:32:25 2011
@@ -1759,11 +1759,14 @@
     if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
         Op.getOperand(0).getValueType().isFloatingPoint() &&
         !Op.getOperand(0).getValueType().isVector()) {
-      if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) {
+      if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) {
+        EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ?
+          Op.getValueType() : MVT::i32;
         // Make a FGETSIGN + SHL to move the sign bit into the appropriate
         // place.  We expect the SHL to be eliminated by other optimizations.
-        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(),
-                                         Op.getOperand(0));
+        SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
+        if (Ty != Op.getValueType())
+          Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
         unsigned ShVal = Op.getValueType().getSizeInBits()-1;
         SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
         return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,