[llvm-commits] [llvm] r132385 - /llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
Andrew Trick
atrick at apple.com
Tue May 31 20:27:56 PDT 2011
Author: atrick
Date: Tue May 31 22:27:56 2011
New Revision: 132385
URL: http://llvm.org/viewvc/llvm-project?rev=132385&view=rev
Log:
Add an issue width check to the postRA scheduler. Patch by Max Kazakov!
For targets with no itinerary (x86) it is a nop by default. For
targets with issue width already expressed in the itinerary (ARM) it
bypasses a scoreboard check but otherwise does not affect the
schedule. It does make the code more consistent and complete and
allows new targets to specify their issue width in an arbitrary way.
Modified:
llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=132385&r1=132384&r2=132385&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue May 31 22:27:56 2011
@@ -661,6 +661,12 @@
ScheduleNodeTopDown(FoundSUnit, CurCycle);
HazardRec->EmitInstruction(FoundSUnit);
CycleHasInsts = true;
+ if (HazardRec->atIssueLimit()) {
+ DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
+ HazardRec->AdvanceCycle();
+ ++CurCycle;
+ CycleHasInsts = false;
+ }
} else {
if (CycleHasInsts) {
DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
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