[llvm-commits] [llvm] r132276 - /llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td

[Rafael Espindola]

Author: rafael
Date: Sat May 28 22:17:01 2011
New Revision: 132276

URL: http://llvm.org/viewvc/llvm-project?rev=132276&view=rev
Log:
Dwarf register 0 is r0, remove incorrect entries.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=132276&r1=132275&r2=132276&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Sat May 28 22:17:01 2011
@@ -261,7 +261,7 @@
 // Carry bit.  In the architecture this is really bit 0 of the XER register
 // (which really is SPR register 1);  this is the only bit interesting to a
 // compiler.
-def CARRY: SPR<1, "ca">, DwarfRegNum<[0]>;
+def CARRY: SPR<1, "ca">;
 
 // FP rounding mode:  bits 30 and 31 of the FP status and control register
 // This is not allocated as a normal register; it appears only in
@@ -271,7 +271,7 @@
 // return and call instructions are described as Uses of RM, so instructions
 // that do nothing but change RM will not get deleted.
 // Also, in the architecture it is not really a SPR; 512 is arbitrary.
-def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>;
+def RM: SPR<512, "**ROUNDING MODE**">;
 
 /// Register classes
 // Allocate volatiles first