[llvm-commits] [llvm] r132024 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp test/CodeGen/ARM/arm-modifier.ll

[Eric Christopher]

Author: echristo
Date: Tue May 24 18:27:13 2011
New Revision: 132024

URL: http://llvm.org/viewvc/llvm-project?rev=132024&view=rev
Log:
Implement the arm 'L' asm modifier.

Part of rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/test/CodeGen/ARM/arm-modifier.ll

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=132024&r1=132023&r2=132024&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue May 24 18:27:13 2011
@@ -415,13 +415,17 @@
         (((Reg % 2) == 1) ? "[0]" : "[1]");
         return false;
       }
-      // Fallthrough to unsupported.
+      return true;
     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
       if (!MI->getOperand(OpNum).isImm())
         return true;
       O << ~(MI->getOperand(OpNum).getImm());
       return false;
     case 'L': // The low 16 bits of an immediate constant.
+      if (!MI->getOperand(OpNum).isImm())
+        return true;
+      O << (MI->getOperand(OpNum).getImm() & 0xffff);
+      return false;
     case 'm': // The base register of a memory operand.
     case 'M': // A register range suitable for LDM/STM.
     case 'p': // The high single-precision register of a VFP double-precision

Modified: llvm/trunk/test/CodeGen/ARM/arm-modifier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-modifier.ll?rev=132024&r1=132023&r2=132024&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-modifier.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-modifier.ll Tue May 24 18:27:13 2011
@@ -21,3 +21,11 @@
 call void asm sideeffect ".word ${0:B} \0A\09", "i"(i32 0) nounwind, !srcloc !0
 ret void
 }
+
+define void @f1() nounwind ssp {
+entry:
+; CHECK: f1
+; CHECK: .word 65535
+call void asm sideeffect ".word ${0:L} \0A\09", "i"(i32 -1) nounwind, !srcloc !0
+ret void
+}