[llvm-commits] [llvm] r132011 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp test/CodeGen/ARM/arm-modifier.ll

[Eric Christopher]

Author: echristo
Date: Tue May 24 17:10:34 2011
New Revision: 132011

URL: http://llvm.org/viewvc/llvm-project?rev=132011&view=rev
Log:
Add support for the arm 'y' asm modifier.

Fixes part of rdar://9444657

Added:
    llvm/trunk/test/CodeGen/ARM/arm-modifier.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=132011&r1=132010&r2=132011&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue May 24 17:10:34 2011
@@ -404,6 +404,18 @@
     case 'q': // Print a NEON quad precision register.
       printOperand(MI, OpNum, O);
       return false;
+    case 'y': // Print a VFP single precision register as indexed double.
+      // This uses the ordering of the alias table to get the first 'd' register
+      // that overlaps the 's' register. Also, s0 is an odd register, hence the
+      // odd modulus check below.
+      if (MI->getOperand(OpNum).isReg()) {
+        unsigned Reg = MI->getOperand(OpNum).getReg();
+        const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
+        O << ARMInstPrinter::getRegisterName(TRI->getAliasSet(Reg)[0]) <<
+        (((Reg % 2) == 1) ? "[0]" : "[1]");
+        return false;
+      }
+      // Fallthrough to unsupported.
     case 'Q':
     case 'R':
     case 'H':

Added: llvm/trunk/test/CodeGen/ARM/arm-modifier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-modifier.ll?rev=132011&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-modifier.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/arm-modifier.ll Tue May 24 17:10:34 2011
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=arm -mattr=+vfp2
+
+define i32 @foo(float %scale, float %scale2) nounwind ssp {
+entry:
+  %scale.addr = alloca float, align 4
+  %scale2.addr = alloca float, align 4
+  store float %scale, float* %scale.addr, align 4
+  store float %scale2, float* %scale2.addr, align 4
+  %tmp = load float* %scale.addr, align 4
+  %tmp1 = load float* %scale2.addr, align 4
+  call void asm sideeffect "vmul.f32    q0, q0, ${0:y} \0A\09vmul.f32    q1, q1, ${0:y} \0A\09vmul.f32    q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind, !srcloc !0
+  ret i32 0
+}
+
+!0 = metadata !{i32 56, i32 89, i32 128, i32 168}