[llvm-commits] [llvm] r131915 - in /llvm/trunk: lib/Target/Mips/MipsFrameLowering.cpp lib/Target/Mips/MipsFrameLowering.h lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsMachineFunction.h lib/Target/Mips/MipsRegisterInfo.cpp test/CodeGen
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Mon May 23 13:36:33 PDT 2011
Nice! Thanks for doing that! :)
On Mon, May 23, 2011 at 5:16 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Mon May 23 15:16:59 2011
> New Revision: 131915
>
> URL: http://llvm.org/viewvc/llvm-project?rev=131915&view=rev
> Log:
> Change StackDirection from StackGrowsUp to StackGrowsDown.
>
> The following improvements are accomplished as a result of applying this patch:
> - Fixed frame objects' offsets (relative to either the virtual frame pointer or
> the stack pointer) are set before instruction selection is completed. There is
> no need to wait until Prologue/Epilogue Insertion is run to set them.
> - Calculation of final offsets of fixed frame objects is straightforward. It is
> no longer necessary to assign negative offsets to fixed objects for incoming
> arguments in order to distinguish them from the others.
> - Since a fixed object has its relative offset set during instruction
> selection, there is no need to conservatively set its alignment to 4.
> - It is no longer necessary to reorder non-fixed frame objects in
> MipsFrameLowering::adjustMipsStackFrame.
>
>
> Modified:
> llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsFrameLowering.h
> llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
> llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
>
> Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=131915&r1=131914&r2=131915&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Mon May 23 15:16:59 2011
> @@ -87,102 +87,13 @@
> return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
> }
>
> -void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const {
> - MachineFrameInfo *MFI = MF.getFrameInfo();
> - MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
> - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
> - unsigned StackAlign = getStackAlignment();
> - unsigned RegSize = STI.isGP32bit() ? 4 : 8;
> - bool HasGP = MipsFI->needGPSaveRestore();
> -
> - // Min and Max CSI FrameIndex.
> - int MinCSFI = -1, MaxCSFI = -1;
> -
> - // See the description at MipsMachineFunction.h
> - int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1;
> -
> - // Replace the dummy '0' SPOffset by the negative offsets, as explained on
> - // LowerFormalArguments. Leaving '0' for while is necessary to avoid the
> - // approach done by calculateFrameObjectOffsets to the stack frame.
> - MipsFI->adjustLoadArgsFI(MFI);
> - MipsFI->adjustStoreVarArgsFI(MFI);
> -
> - // It happens that the default stack frame allocation order does not directly
> - // map to the convention used for mips. So we must fix it. We move the callee
> - // save register slots after the local variables area, as described in the
> - // stack frame above.
> - unsigned CalleeSavedAreaSize = 0;
> - if (!CSI.empty()) {
> - MinCSFI = CSI[0].getFrameIdx();
> - MaxCSFI = CSI[CSI.size()-1].getFrameIdx();
> - }
> - for (unsigned i = 0, e = CSI.size(); i != e; ++i)
> - CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx());
> -
> - unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize)
> - : (STI.isABI_O32() ? 16 : 0);
> -
> - // Adjust local variables. They should come on the stack right
> - // after the arguments.
> - int LastOffsetFI = -1;
> - for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) {
> - if (i >= MinCSFI && i <= MaxCSFI)
> - continue;
> - if (MFI->isDeadObjectIndex(i))
> - continue;
> - unsigned Offset =
> - StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize;
> - if (LastOffsetFI == -1)
> - LastOffsetFI = i;
> - if (Offset > MFI->getObjectOffset(LastOffsetFI))
> - LastOffsetFI = i;
> - MFI->setObjectOffset(i, Offset);
> - }
> -
> - // Adjust CPU Callee Saved Registers Area. Registers RA and FP must
> - // be saved in this CPU Area. This whole area must be aligned to the
> - // default Stack Alignment requirements.
> - if (LastOffsetFI >= 0)
> - StackOffset = MFI->getObjectOffset(LastOffsetFI)+
> - MFI->getObjectSize(LastOffsetFI);
> - StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
> -
> - for (unsigned i = 0, e = CSI.size(); i != e ; ++i) {
> - unsigned Reg = CSI[i].getReg();
> - if (!Mips::CPURegsRegisterClass->contains(Reg))
> - break;
> - MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
> - TopCPUSavedRegOff = StackOffset;
> - StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
> - }
> -
> - StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
> -
> - // Adjust FPU Callee Saved Registers Area. This Area must be
> - // aligned to the default Stack Alignment requirements.
> - for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
> - unsigned Reg = CSI[i].getReg();
> - if (Mips::CPURegsRegisterClass->contains(Reg))
> - continue;
> - MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset);
> - TopFPUSavedRegOff = StackOffset;
> - StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx());
> - }
> - StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign);
> -
> - // Update frame info
> - MFI->setStackSize(StackOffset);
> -
> - // Recalculate the final tops offset. The final values must be '0'
> - // if there isn't a callee saved register for CPU or FPU, otherwise
> - // a negative offset is needed.
> - if (TopCPUSavedRegOff >= 0)
> - MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset);
> -
> - if (TopFPUSavedRegOff >= 0)
> - MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset);
> +bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
> + return true;
> }
>
> +static unsigned AlignOffset(unsigned Offset, unsigned Align) {
> + return (Offset + Align - 1) / Align * Align;
> +}
>
> // expand pair of register and immediate if the immediate doesn't fit in the
> // 16-bit offset field.
> @@ -238,12 +149,18 @@
> int NewImm = 0;
> bool ATUsed;
>
> - // Get the right frame order for Mips.
> - adjustMipsStackFrame(MF);
> -
> - // Get the number of bytes to allocate from the FrameInfo.
> - unsigned StackSize = MFI->getStackSize();
> + // First, compute final stack size.
> + unsigned RegSize = STI.isGP32bit() ? 4 : 8;
> + unsigned StackAlign = getStackAlignment();
> + unsigned LocalVarAreaOffset = MipsFI->needGPSaveRestore() ?
> + (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) :
> + MFI->getMaxCallFrameSize();
> + unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) +
> + AlignOffset(MFI->getStackSize(), StackAlign);
>
> + // Update stack size
> + MFI->setStackSize(StackSize);
> +
> BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
>
> // TODO: check need from GP here.
> @@ -282,7 +199,7 @@
> // Restore GP from the saved stack location
> if (MipsFI->needGPSaveRestore())
> BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE))
> - .addImm(MipsFI->getGPStackOffset());
> + .addImm(MFI->getObjectOffset(MipsFI->getGPFI()));
> }
>
> void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
> @@ -349,10 +266,3 @@
> else
> MRI.setPhysRegUnused(Mips::RA);
> }
> -
> -void MipsFrameLowering::
> -processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
> - const MipsRegisterInfo *RegInfo =
> - static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
> - RegInfo->processFunctionBeforeFrameFinalized(MF);
> -}
>
> Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.h?rev=131915&r1=131914&r2=131915&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.h Mon May 23 15:16:59 2011
> @@ -27,11 +27,10 @@
>
> public:
> explicit MipsFrameLowering(const MipsSubtarget &sti)
> - // FIXME: Is this correct at all?
> - : TargetFrameLowering(StackGrowsUp, 8, 0), STI(sti) {
> + : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
> }
>
> - void adjustMipsStackFrame(MachineFunction &MF) const;
> + bool targetHandlesStackFrameRounding() const;
>
> /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
> /// the function.
> @@ -42,7 +41,6 @@
>
> void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
> RegScavenger *RS) const;
> - void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
> };
>
> } // End llvm namespace
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=131915&r1=131914&r2=131915&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon May 23 15:16:59 2011
> @@ -1069,7 +1069,7 @@
>
> // Create GP frame object if this is the first call.
> // SPOffset will be updated after call frame size is known.
> - if (IsPIC && MipsFI->getGPStackOffset() == -1)
> + if (IsPIC && !MipsFI->getGPFI())
> MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
>
> int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
> @@ -1124,10 +1124,10 @@
> // This guarantees that when allocating Local Area the firsts
> // 16 bytes which are alwayes reserved won't be overwritten
> // if O32 ABI is used. For EABI the first address is zero.
> + unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
> NextStackOffset = VA.getLocMemOffset();
> - LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
> - NextStackOffset, true);
> - NextStackOffset += VA.getValVT().getSizeInBits()/8;
> + LastFI = MFI->CreateFixedObject(ArgSize, NextStackOffset, true);
> + NextStackOffset += ArgSize;
>
> SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
>
> @@ -1243,7 +1243,8 @@
> unsigned StackAlignment = TFL->getStackAlignment();
> NextStackOffset = (NextStackOffset + StackAlignment - 1) /
> StackAlignment * StackAlignment;
> - MipsFI->setGPStackOffset(NextStackOffset);
> + int GPFI = MipsFI->getGPFI();
> + MFI->setObjectOffset(GPFI, NextStackOffset);
> }
> }
>
> @@ -1405,9 +1406,9 @@
> // be used on emitPrologue) to avoid mis-calc of the first stack
> // offset on PEI::calculateFrameObjectOffsets.
> unsigned ArgSize = VA.getValVT().getSizeInBits()/8;
> - NextStackOffset = VA.getLocMemOffset() + ArgSize;
> - LastFI = MFI->CreateFixedObject(ArgSize, 0, true);
> - MipsFI->recordLoadArgsFI(LastFI, -(4 + VA.getLocMemOffset()));
> + NextStackOffset = VA.getLocMemOffset();
> + LastFI = MFI->CreateFixedObject(ArgSize, NextStackOffset, true);
> + NextStackOffset += ArgSize;
>
> // Create load nodes to retrieve arguments from the stack
> SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
> @@ -1449,8 +1450,7 @@
> unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
> SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
>
> - LastFI = MFI->CreateFixedObject(4, 0, true);
> - MipsFI->recordStoreVarArgsFI(LastFI, -(4+(ArgRegEnd-Mips::A0)*4));
> + LastFI = MFI->CreateFixedObject(4, (ArgRegEnd-Mips::A0)*4, true);
> SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
> OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
> MachinePointerInfo(),
> @@ -1458,26 +1458,20 @@
>
> // Record the frame index of the first variable argument
> // which is a value necessary to VASTART.
> - if (!MipsFI->getVarArgsFrameIndex()) {
> - MFI->setObjectAlignment(LastFI, 4);
> + if (!MipsFI->getVarArgsFrameIndex())
> MipsFI->setVarArgsFrameIndex(LastFI);
> - }
> }
> } else {
> // Last named formal argument is in register Mips::A3, and the first
> // variable argument is on stack. Record the frame index of the first
> // variable argument.
> - LastFI = MFI->CreateFixedObject(4, 0, true);
> - MFI->setObjectAlignment(LastFI, 4);
> - MipsFI->recordStoreVarArgsFI(LastFI, -20);
> + LastFI = MFI->CreateFixedObject(4, 16, true);
> MipsFI->setVarArgsFrameIndex(LastFI);
> }
> } else {
> // Last named formal argument and all the variable arguments are passed
> // on stack. Record the frame index of the first variable argument.
> - LastFI = MFI->CreateFixedObject(4, 0, true);
> - MFI->setObjectAlignment(LastFI, 4);
> - MipsFI->recordStoreVarArgsFI(LastFI, -(4+NextStackOffset));
> + LastFI = MFI->CreateFixedObject(4, NextStackOffset, true);
> MipsFI->setVarArgsFrameIndex(LastFI);
> }
> }
>
> Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=131915&r1=131914&r2=131915&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Mon May 23 15:16:59 2011
> @@ -34,35 +34,6 @@
> int CPUTopSavedRegOff;
> int FPUTopSavedRegOff;
>
> - /// MipsFIHolder - Holds a FrameIndex and it's Stack Pointer Offset
> - struct MipsFIHolder {
> -
> - int FI;
> - int SPOffset;
> -
> - MipsFIHolder(int FrameIndex, int StackPointerOffset)
> - : FI(FrameIndex), SPOffset(StackPointerOffset) {}
> - };
> -
> - /// When PIC is used the GP must be saved on the stack on the function
> - /// prologue and must be reloaded from this stack location after every
> - /// call. A reference to its stack location and frame index must be kept
> - /// to be used on emitPrologue and processFunctionBeforeFrameFinalized.
> - MipsFIHolder GPHolder;
> -
> - /// On LowerFormalArguments the stack size is unknown, so the Stack
> - /// Pointer Offset calculation of "not in register arguments" must be
> - /// postponed to emitPrologue.
> - SmallVector<MipsFIHolder, 16> FnLoadArgs;
> - bool HasLoadArgs;
> -
> - // When VarArgs, we must write registers back to caller stack, preserving
> - // on register arguments. Since the stack size is unknown on
> - // LowerFormalArguments, the Stack Pointer Offset calculation must be
> - // postponed to emitPrologue.
> - SmallVector<MipsFIHolder, 4> FnStoreVarArgs;
> - bool HasStoreVarArgs;
> -
> /// SRetReturnReg - Some subtargets require that sret lowering includes
> /// returning the value of the returned struct in a register. This field
> /// holds the virtual register into which the sret argument is passed.
> @@ -88,8 +59,7 @@
> public:
> MipsFunctionInfo(MachineFunction& MF)
> : CPUTopSavedRegOff(0),
> - FPUTopSavedRegOff(0), GPHolder(-1,-1), HasLoadArgs(false),
> - HasStoreVarArgs(false), SRetReturnReg(0), GlobalBaseReg(0),
> + FPUTopSavedRegOff(0), SRetReturnReg(0), GlobalBaseReg(0),
> VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
> OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), HasCall(false),
> MaxCallFrameSize(-1)
> @@ -116,36 +86,11 @@
> OutArgFIRange.second = LastFI;
> }
>
> - int getGPStackOffset() const { return GPHolder.SPOffset; }
> - int getGPFI() const { return GPHolder.FI; }
> - void setGPStackOffset(int Off) { GPHolder.SPOffset = Off; }
> - void setGPFI(int FI) { GPHolder.FI = FI; }
> - bool needGPSaveRestore() const { return GPHolder.SPOffset != -1; }
> + int getGPFI() const { return GPFI; }
> + void setGPFI(int FI) { GPFI = FI; }
> + bool needGPSaveRestore() const { return getGPFI(); }
> bool isGPFI(int FI) const { return GPFI && GPFI == FI; }
>
> - bool hasLoadArgs() const { return HasLoadArgs; }
> - bool hasStoreVarArgs() const { return HasStoreVarArgs; }
> -
> - void recordLoadArgsFI(int FI, int SPOffset) {
> - if (!HasLoadArgs) HasLoadArgs=true;
> - FnLoadArgs.push_back(MipsFIHolder(FI, SPOffset));
> - }
> - void recordStoreVarArgsFI(int FI, int SPOffset) {
> - if (!HasStoreVarArgs) HasStoreVarArgs=true;
> - FnStoreVarArgs.push_back(MipsFIHolder(FI, SPOffset));
> - }
> -
> - void adjustLoadArgsFI(MachineFrameInfo *MFI) const {
> - if (!hasLoadArgs()) return;
> - for (unsigned i = 0, e = FnLoadArgs.size(); i != e; ++i)
> - MFI->setObjectOffset( FnLoadArgs[i].FI, FnLoadArgs[i].SPOffset );
> - }
> - void adjustStoreVarArgsFI(MachineFrameInfo *MFI) const {
> - if (!hasStoreVarArgs()) return;
> - for (unsigned i = 0, e = FnStoreVarArgs.size(); i != e; ++i)
> - MFI->setObjectOffset( FnStoreVarArgs[i].FI, FnStoreVarArgs[i].SPOffset );
> - }
> -
> unsigned getSRetReturnReg() const { return SRetReturnReg; }
> void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=131915&r1=131914&r2=131915&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon May 23 15:16:59 2011
> @@ -98,22 +98,22 @@
> {
> // Mips callee-save register range is $16-$23, $f20-$f30
> static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
> - Mips::S0, Mips::S1, Mips::S2, Mips::S3,
> - Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::FP, Mips::RA,
> - Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
> - Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
> + Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26,
> + Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20,
> + Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
> + Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
> };
>
> static const unsigned BitMode32CalleeSavedRegs[] = {
> - Mips::S0, Mips::S1, Mips::S2, Mips::S3,
> - Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::FP, Mips::RA,
> - Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
> + Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20,
> + Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
> + Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
> };
>
> static const unsigned Mips32CalleeSavedRegs[] = {
> - Mips::S0, Mips::S1, Mips::S2, Mips::S3,
> - Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::FP, Mips::RA,
> - Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, 0
> + Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10,
> + Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4,
> + Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0
> };
>
> if (Subtarget.isSingleFloat())
> @@ -182,9 +182,19 @@
> << "spOffset : " << spOffset << "\n"
> << "stackSize : " << stackSize << "\n");
>
> - // as explained on LowerFormalArguments, detect negative offsets
> - // and adjust SPOffsets considering the final stack size.
> - int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
> + int Offset;
> +
> + // Calculate final offset.
> + // - There is no need to change the offset if the frame object is an outgoing
> + // argument or a $gp restore location,
> + // - If the frame object is any of the following, its offset must be adjusted
> + // by adding the size of the stack:
> + // incoming argument, callee-saved register location or local variable.
> + if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex))
> + Offset = spOffset;
> + else
> + Offset = spOffset + stackSize;
> +
> Offset += MI.getOperand(i-1).getImm();
>
> DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
> @@ -247,15 +257,6 @@
> MI.getOperand(i-1).ChangeToImmediate(NewImm);
> }
>
> -void MipsRegisterInfo::
> -processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
> - // Set the stack offset where GP must be saved/loaded from.
> - MachineFrameInfo *MFI = MF.getFrameInfo();
> - MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
> - if (MipsFI->needGPSaveRestore())
> - MFI->setObjectOffset(MipsFI->getGPFI(), MipsFI->getGPStackOffset());
> -}
> -
> unsigned MipsRegisterInfo::
> getRARegister() const {
> return Mips::RA;
>
> Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=131915&r1=131914&r2=131915&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Mon May 23 15:16:59 2011
> @@ -29,11 +29,11 @@
> ret i32 %tmp
>
> ; CHECK: va1:
> -; CHECK: addiu $sp, $sp, -32
> -; CHECK: sw $7, 44($sp)
> -; CHECK: sw $6, 40($sp)
> -; CHECK: sw $5, 36($sp)
> -; CHECK: lw $2, 36($sp)
> +; CHECK: addiu $sp, $sp, -16
> +; CHECK: sw $7, 28($sp)
> +; CHECK: sw $6, 24($sp)
> +; CHECK: sw $5, 20($sp)
> +; CHECK: lw $2, 20($sp)
> }
>
> ; check whether the variable double argument will be accessed from the 8-byte
> @@ -55,11 +55,11 @@
> ret double %tmp
>
> ; CHECK: va2:
> -; CHECK: addiu $sp, $sp, -40
> -; CHECK: sw $7, 52($sp)
> -; CHECK: sw $6, 48($sp)
> -; CHECK: sw $5, 44($sp)
> -; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
> +; CHECK: addiu $sp, $sp, -16
> +; CHECK: sw $7, 28($sp)
> +; CHECK: sw $6, 24($sp)
> +; CHECK: sw $5, 20($sp)
> +; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
> ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
> ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
> ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
> @@ -83,10 +83,10 @@
> ret i32 %tmp
>
> ; CHECK: va3:
> -; CHECK: addiu $sp, $sp, -40
> -; CHECK: sw $7, 52($sp)
> -; CHECK: sw $6, 48($sp)
> -; CHECK: lw $2, 48($sp)
> +; CHECK: addiu $sp, $sp, -16
> +; CHECK: sw $7, 28($sp)
> +; CHECK: sw $6, 24($sp)
> +; CHECK: lw $2, 24($sp)
> }
>
> ; double
> @@ -106,14 +106,11 @@
> ret double %tmp
>
> ; CHECK: va4:
> -; CHECK: addiu $sp, $sp, -48
> -; CHECK: sw $7, 60($sp)
> -; CHECK: sw $6, 56($sp)
> -; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
> -; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
> -; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
> -; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
> -; CHECK: ldc1 $f0, 0($[[R3]])
> +; CHECK: addiu $sp, $sp, -24
> +; CHECK: sw $7, 36($sp)
> +; CHECK: sw $6, 32($sp)
> +; CHECK: addiu ${{[0-9]+}}, $sp, 32
> +; CHECK: ldc1 $f0, 32($sp)
> }
>
> ; int
> @@ -137,9 +134,9 @@
> ret i32 %tmp
>
> ; CHECK: va5:
> -; CHECK: addiu $sp, $sp, -40
> -; CHECK: sw $7, 52($sp)
> -; CHECK: lw $2, 52($sp)
> +; CHECK: addiu $sp, $sp, -24
> +; CHECK: sw $7, 36($sp)
> +; CHECK: lw $2, 36($sp)
> }
>
> ; double
> @@ -163,9 +160,9 @@
> ret double %tmp
>
> ; CHECK: va6:
> -; CHECK: addiu $sp, $sp, -48
> -; CHECK: sw $7, 60($sp)
> -; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
> +; CHECK: addiu $sp, $sp, -24
> +; CHECK: sw $7, 36($sp)
> +; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
> ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
> ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
> ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
> @@ -191,8 +188,8 @@
> ret i32 %tmp
>
> ; CHECK: va7:
> -; CHECK: addiu $sp, $sp, -40
> -; CHECK: lw $2, 56($sp)
> +; CHECK: addiu $sp, $sp, -24
> +; CHECK: lw $2, 40($sp)
> }
>
> ; double
> @@ -214,12 +211,9 @@
> ret double %tmp
>
> ; CHECK: va8:
> -; CHECK: addiu $sp, $sp, -48
> -; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
> -; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
> -; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
> -; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
> -; CHECK: ldc1 $f0, 0($[[R3]])
> +; CHECK: addiu $sp, $sp, -32
> +; CHECK: addiu ${{[0-9]+}}, $sp, 48
> +; CHECK: ldc1 $f0, 48($sp)
> }
>
> ; int
> @@ -243,8 +237,8 @@
> ret i32 %tmp
>
> ; CHECK: va9:
> -; CHECK: addiu $sp, $sp, -56
> -; CHECK: lw $2, 76($sp)
> +; CHECK: addiu $sp, $sp, -32
> +; CHECK: lw $2, 52($sp)
> }
>
> ; double
> @@ -268,8 +262,8 @@
> ret double %tmp
>
> ; CHECK: va10:
> -; CHECK: addiu $sp, $sp, -56
> -; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
> +; CHECK: addiu $sp, $sp, -32
> +; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
> ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
> ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
> ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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