[llvm-commits] [llvm] r131689 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-ret-ext.ll
Eli Friedman
eli.friedman at gmail.com
Thu May 19 15:16:13 PDT 2011
Author: efriedma
Date: Thu May 19 17:16:13 2011
New Revision: 131689
URL: http://llvm.org/viewvc/llvm-project?rev=131689&view=rev
Log:
Add fast-isel support for zeroext and signext ret instructions on x86.
Added:
llvm/trunk/test/CodeGen/X86/fast-isel-ret-ext.ll
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131689&r1=131688&r2=131689&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu May 19 17:16:13 2011
@@ -722,18 +722,38 @@
// Only handle register returns for now.
if (!VA.isRegLoc())
return false;
- // TODO: For now, don't try to handle cases where getLocInfo()
- // says Full but the types don't match.
- if (TLI.getValueType(RV->getType()) != VA.getValVT())
- return false;
// The calling-convention tables for x87 returns don't tell
// the whole story.
if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
return false;
- // Make the copy.
unsigned SrcReg = Reg + VA.getValNo();
+ EVT SrcVT = TLI.getValueType(RV->getType());
+ EVT DstVT = VA.getValVT();
+ // Special handling for extended integers.
+ if (SrcVT != DstVT) {
+ if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
+ return false;
+
+ if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
+ return false;
+
+ assert(DstVT == MVT::i32 && "X86 should always ext to i32");
+
+ if (SrcVT == MVT::i1) {
+ if (Outs[0].Flags.isSExt())
+ return false;
+ SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
+ SrcVT = MVT::i8;
+ }
+ unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
+ ISD::SIGN_EXTEND;
+ SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
+ SrcReg, /*TODO: Kill=*/false);
+ }
+
+ // Make the copy.
unsigned DstReg = VA.getLocReg();
const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
// Avoid a cross-class copy. This is very unlikely.
Added: llvm/trunk/test/CodeGen/X86/fast-isel-ret-ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-ret-ext.ll?rev=131689&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-ret-ext.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-ret-ext.ll Thu May 19 17:16:13 2011
@@ -0,0 +1,38 @@
+; RUN: llc < %s -O0 -fast-isel-abort -mtriple i686-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -O0 -fast-isel-abort -mtriple x86_64-apple-darwin10 | FileCheck %s
+
+define zeroext i8 @test1(i32 %y) nounwind {
+ %conv = trunc i32 %y to i8
+ ret i8 %conv
+ ; CHECK: test1:
+ ; CHECK: movzbl {{.*}}, %eax
+}
+
+define signext i8 @test2(i32 %y) nounwind {
+ %conv = trunc i32 %y to i8
+ ret i8 %conv
+ ; CHECK: test2:
+ ; CHECK: movsbl {{.*}}, %eax
+}
+
+define zeroext i16 @test3(i32 %y) nounwind {
+ %conv = trunc i32 %y to i16
+ ret i16 %conv
+ ; CHECK: test3:
+ ; CHECK: movzwl {{.*}}, %eax
+}
+
+define signext i16 @test4(i32 %y) nounwind {
+ %conv = trunc i32 %y to i16
+ ret i16 %conv
+ ; CHECK: test4:
+ ; CHECK: movswl {{.*}}, %eax
+}
+
+define zeroext i1 @test5(i32 %y) nounwind {
+ %conv = trunc i32 %y to i1
+ ret i1 %conv
+ ; CHECK: test5:
+ ; CHECK: andb $1
+ ; CHECK: movzbl {{.*}}, %eax
+}
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