[llvm-commits] [llvm] r131664 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/crc64.ll

[Evan Cheng]

Author: evancheng
Date: Thu May 19 13:57:12 2011
New Revision: 131664

URL: http://llvm.org/viewvc/llvm-project?rev=131664&view=rev
Log:
crc32 with 64-bit output zeros upper 32-bits. rdar://9467055

Added:
    llvm/trunk/test/CodeGen/X86/crc64.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131664&r1=131663&r2=131664&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu May 19 13:57:12 2011
@@ -10939,6 +10939,19 @@
     KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
                                        Mask.getBitWidth() - 1);
     break;
+
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    switch (IntNo) {
+      default: break;
+      case Intrinsic::x86_sse42_crc64_8:
+      case Intrinsic::x86_sse42_crc64_64:
+        // crc32 with 64-bit destination zeros high 32-bit.
+        KnownZero |= APInt::getHighBitsSet(64, 32);
+        break;
+    }
+    break;
+  }
   }
 }
 

Added: llvm/trunk/test/CodeGen/X86/crc64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/crc64.ll?rev=131664&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/crc64.ll (added)
+++ llvm/trunk/test/CodeGen/X86/crc64.ll Thu May 19 13:57:12 2011
@@ -0,0 +1,19 @@
+; RUN: llc < %s -march=x86-64 -mattr=sse42 | FileCheck %s
+
+; crc32 with 64-bit destination zeros high 32-bit.
+; rdar://9467055
+
+define i64 @t() nounwind {
+entry:
+; CHECK: t:
+; CHECK: crc32q
+; CHECK-NOT: mov
+; CHECK-NEXT: crc32q
+  %0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
+  %1 = and i64 %0, 4294967295
+  %2 = tail call i64 @llvm.x86.sse42.crc64.64(i64 %1, i64 4) nounwind
+  %3 = and i64 %2, 4294967295
+  ret i64 %3
+}
+
+declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone