[llvm-commits] [llvm] r131471 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h

[Eli Friedman]

Author: efriedma
Date: Tue May 17 13:02:22 2011
New Revision: 131471

URL: http://llvm.org/viewvc/llvm-project?rev=131471&view=rev
Log:
Clean up the mess created by r131467+r131469.


Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131471&r1=131470&r2=131471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue May 17 13:02:22 2011
@@ -2104,8 +2104,6 @@
         }
         if (ShadowReg)
           RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
-      } else {        // Usual case: not byval.
-        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
       }
     } else if (!IsSibcall && (!isTailCall || isByVal)) {
       assert(VA.isMemLoc());
@@ -11063,13 +11061,6 @@
   return SDValue();
 }
 
-/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
-/// generation and convert it from being a bunch of shuffles and extracts
-/// to a simple store and scalar loads to extract the elements.
-static SDValue PerformVectorZeroExtendCombine(SDNode *N, SelectionDAG &DAG) {
-  return SDValue();
-}
-
 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
                                     const X86Subtarget *Subtarget) {
@@ -12130,9 +12121,6 @@
   case X86ISD::VZEXT_MOVL:  return PerformVZEXT_MOVLCombine(N, DAG);
   case ISD::ZERO_EXTEND:    return PerformZExtCombine(N, DAG);
   case X86ISD::SETCC:       return PerformSETCCCombine(N, DAG);
-  case X86ISD::PMOVZXBW:
-  case X86ISD::PMOVZXWD:
-  case X86ISD::PMOVZXDQ:    return PerformVectorZeroExtendCombine(N, DAG);
   case X86ISD::SHUFPS:      // Handle all target specific shuffles
   case X86ISD::SHUFPD:
   case X86ISD::PALIGN:

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=131471&r1=131470&r2=131471&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue May 17 13:02:22 2011
@@ -263,10 +263,6 @@
       PUNPCKHDQ,
       PUNPCKHQDQ,
 
-      PMOVZXBW,
-      PMOVZXWD,
-      PMOVZXDQ,
-
       // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
       // according to %al. An operator is needed so that this can be expanded
       // with control flow.