[llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

[Duncan Sands]

Hi Nadav,

> +    setOperationAction(ISD::SRA,               MVT::v4i32, Custom);
> +    setOperationAction(ISD::SRA,               MVT::v8i16, Custom);

so there is no v2i64 arithmetic right shift?

> +  // Must have SSE2
> +  if(! Subtarget->hasSSE2()) return SDValue();

There should be a space between "if" and "(" and no space after "!".  This
problem occurs also in the SSE 4.1 test.

> -  if (VT == MVT::v4i32) {
> +  // Optimize shl/srl with constant shift amount

There should be a full stop at the end of the comment.  The comment doesn't
mention sra but it is handled too.

Otherwise it looks OK to me.

Ciao, Duncan.