[llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

[Rotem, Nadav]

Hi Eli, 

Thanks for the quick reply. When I worked on implementing the 'vector-select' feature, I found several cases where PerformShiftCombine was unable to convert vector shifts to x86-shifts. Often, the shift amount operand (originally expresses as a BUILD_VECTOR) was already lowered to a constant pool read. This scenario is likely to happen in places where the op legalizer creates new shift instructions. This happened to me when I implemented the operation legalization of vector SIGN_EXTEND_INREG. I assumed that this is a good place to add the vector-shift lowering because this is where vector-SHL was implemented.

Thanks,
Nadav




-----Original Message-----
From: Eli Friedman [mailto:eli.friedman at gmail.com] 
Sent: Thursday, May 05, 2011 18:24
To: Rotem, Nadav
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [PATCH] A patch to add vector SHL/SRL/SRA support for x86

On Thu, May 5, 2011 at 4:32 AM, Rotem, Nadav <nadav.rotem at intel.com> wrote:
> This patch addresses 9597.

Your testcase passes without your patch.  See PerformShiftCombine in
X86ISelLowering.cpp.  I woiuldn't be opposed to moving that code to
legalization if that works, though.  (I think it will because of the
separation of vector legalization.)

-Eli
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