[llvm-commits] [llvm] r130502 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/CodeGen/Thumb2/thumb2-ror.ll

[Andrew Trick]

Author: atrick
Date: Fri Apr 29 09:18:15 2011
New Revision: 130502

URL: http://llvm.org/viewvc/llvm-project?rev=130502&view=rev
Log:
Teach Thumb2 isel to fold and->rotr ==> ROR.

Generalization of Nate Begeman's patch!

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=130502&r1=130501&r2=130502&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Apr 29 09:18:15 2011
@@ -84,6 +84,11 @@
   return (uint32_t)(~N->getZExtValue()) < 255;
 }], imm_comp_XFORM>;
 
+def lo5AllOne : PatLeaf<(i32 imm), [{
+  // Returns true if all low 5-bits are 1.
+  return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL;
+}]>;
+
 // Define Thumb2 specific addressing modes.
 
 // t2addrmode_imm12  := reg + imm12
@@ -2023,6 +2028,10 @@
 defm t2ASR  : T2I_sh_ir<0b10, "asr", BinOpFrag<(sra  node:$LHS, node:$RHS)>>;
 defm t2ROR  : T2I_sh_ir<0b11, "ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
 
+// (rotr x, (and y, 0x...1f)) ==> (ROR x, y)
+def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)),
+          (t2RORrr rGPR:$lhs, rGPR:$rhs)>;
+
 let Uses = [CPSR] in {
 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
                    "rrx", "\t$Rd, $Rm",

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll?rev=130502&r1=130501&r2=130502&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ror.ll Fri Apr 29 09:18:15 2011
@@ -11,11 +11,13 @@
 }
 
 ; CHECK: f2:
+; CHECK-NOT: and
 ; CHECK: ror
 define i32 @f2(i32 %v, i32 %nbits) {
 entry:
-  %shr = lshr i32 %v, %nbits
-  %sub = sub i32 32, %nbits
+  %and = and i32 %nbits, 31
+  %shr = lshr i32 %v, %and
+  %sub = sub i32 32, %and
   %shl = shl i32 %v, %sub
   %or = or i32 %shl, %shr
   ret i32 %or