[llvm-commits] [llvm] r130008 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td test/MC/Disassembler/ARM/thumb-printf.txt test/MC/Disassembler/ARM/thumb-tests.txt utils/TableGen/ARMDecoderEmitter.cpp
Johnny Chen
johnny.chen at apple.com
Fri Apr 22 12:12:43 PDT 2011
Author: johnny
Date: Fri Apr 22 14:12:43 2011
New Revision: 130008
URL: http://llvm.org/viewvc/llvm-project?rev=130008&view=rev
Log:
Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.
rdar://problem/9267772
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=130008&r1=130007&r2=130008&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Apr 22 14:12:43 2011
@@ -721,6 +721,19 @@
let Inst{7-0} = addr;
}
+// FIXME: Remove this entry when the above ldr.n workaround is fixed.
+// For disassembly use only.
+def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
+ "ldr", "\t$Rt, $addr",
+ [/* disassembly only */]>,
+ T1Encoding<{0,1,0,0,1,?}> {
+ // A6.2 & A8.6.59
+ bits<3> Rt;
+ bits<8> addr;
+ let Inst{10-8} = Rt;
+ let Inst{7-0} = addr;
+}
+
// A8.6.194 & A8.6.192
defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
t_addrmode_is4, AddrModeT1_4,
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt?rev=130008&r1=130007&r2=130008&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt Fri Apr 22 14:12:43 2011
@@ -7,17 +7,17 @@
# CHECK-NEXT: add r3, sp, #20
# CHECK-NEXT: ldr r5, [r3], #4
# CHECK-NEXT: str r3, [sp]
-# CHECK-NEXT: ldr.n r3, #52
+# CHECK-NEXT: ldr r3, #52
# CHECK-NEXT: add r3, pc
# CHECK-NEXT: ldr r0, [r3]
# CHECK-NEXT: ldr r4, [r0]
-# CHECK-NEXT: ldr.n r0, #48
+# CHECK-NEXT: ldr r0, #48
# CHECK-NEXT: add r0, pc
# CHECK-NEXT: ldr r0, [r0]
# CHECK-NEXT: ldr r0, [r0]
# CHECK-NEXT: blx #191548
# CHECK-NEXT: cbnz r0, #6
-# CHECK-NEXT: ldr.n r1, #40
+# CHECK-NEXT: ldr r1, #40
# CHECK-NEXT: add r1, pc
# CHECK-NEXT: ldr r1, [r1]
# CHECK-NEXT: b #0
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=130008&r1=130007&r2=130008&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Fri Apr 22 14:12:43 2011
@@ -30,6 +30,9 @@
# CHECK: ldmia r0!, {r1}
0x02 0xc8
+# CHECK: ldr r5, #432
+0x6c 0x4d
+
# CHECK: str r0, [r3]
0x18 0x60
Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=130008&r1=130007&r2=130008&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Fri Apr 22 14:12:43 2011
@@ -1652,6 +1652,11 @@
Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12")
return false;
+ // FIXME: Use ldr.n to work around a Darwin assembler bug.
+ // Introduce a workaround with tLDRpciDIS opcode.
+ if (Name == "tLDRpci")
+ return false;
+
// Ignore t2LDRDpci, prefer the generic t2LDRDi8, t2LDRD_PRE, t2LDRD_POST.
if (Name == "t2LDRDpci")
return false;
More information about the llvm-commits
mailing list