[llvm-commits] [llvm] r129739 - in /llvm/trunk/test/CodeGen: ARM/fcopysign.ll ARM/inlineasm3.ll Mips/buildpairextractelementf64.ll Thumb/2010-07-15-debugOrdering.ll

[Jakob Stoklund Olesen]

On Apr 18, 2011, at 10:10 PM, Evan Cheng wrote:

> 
> 
> On Apr 18, 2011, at 5:14 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> 
>> Author: stoklund
>> Date: Mon Apr 18 19:14:43 2011
>> New Revision: 129739
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=129739&view=rev
>> Log:
>> Make tests register allocation independent again.
>> 
>> Modified:
>>   llvm/trunk/test/CodeGen/ARM/fcopysign.ll
>>   llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
>>   llvm/trunk/test/CodeGen/Mips/buildpairextractelementf64.ll
>>   llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
>> 
>> Modified: llvm/trunk/test/CodeGen/ARM/fcopysign.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fcopysign.ll?rev=129739&r1=129738&r2=129739&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/fcopysign.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/fcopysign.ll Mon Apr 18 19:14:43 2011
>> @@ -45,10 +45,10 @@
>> entry:
>> ; SOFT: test4:
>> ; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
>> -; SOFT: vcvt.f32.f64 s0, [[REG4]]
>> +; SOFT: vcvt.f32.f64 {{s[0-9]+}}, [[REG4]]
>> ; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
>> ; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
>> -; SOFT: vbsl [[REG5]], [[REG4]], d0
>> +; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
>>  %call80 = tail call double @copysign(double 1.000000e+00, double undef)
>>  %conv81 = fptrunc double %call80 to float
>>  %tmp88 = bitcast float %conv81 to i32
> 
> There is a problem with the change. The s register must be a sub-register of the d register (previously s0 and d0). 

Yes, but unfortunately FileCheck can't express that, it would need to divide the S-register number by 2.

We could add a Lisp interpreter to FileCheck?

/jakob