[llvm-commits] [llvm] r129739 - in /llvm/trunk/test/CodeGen: ARM/fcopysign.ll ARM/inlineasm3.ll Mips/buildpairextractelementf64.ll Thumb/2010-07-15-debugOrdering.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Mon Apr 18 19:14:43 2011
New Revision: 129739

URL: http://llvm.org/viewvc/llvm-project?rev=129739&view=rev
Log:
Make tests register allocation independent again.

Modified:
    llvm/trunk/test/CodeGen/ARM/fcopysign.ll
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
    llvm/trunk/test/CodeGen/Mips/buildpairextractelementf64.ll
    llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll

Modified: llvm/trunk/test/CodeGen/ARM/fcopysign.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fcopysign.ll?rev=129739&r1=129738&r2=129739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fcopysign.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fcopysign.ll Mon Apr 18 19:14:43 2011
@@ -45,10 +45,10 @@
 entry:
 ; SOFT: test4:
 ; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
-; SOFT: vcvt.f32.f64 s0, [[REG4]]
+; SOFT: vcvt.f32.f64 {{s[0-9]+}}, [[REG4]]
 ; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
 ; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
-; SOFT: vbsl [[REG5]], [[REG4]], d0
+; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}
   %call80 = tail call double @copysign(double 1.000000e+00, double undef)
   %conv81 = fptrunc double %call80 to float
   %tmp88 = bitcast float %conv81 to i32

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=129739&r1=129738&r2=129739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Mon Apr 18 19:14:43 2011
@@ -6,7 +6,7 @@
 define void @t() nounwind {
 entry:
 ; CHECK: vmov.I64 q15, #0
-; CHECK: vmov.32 d30[0], r0
+; CHECK: vmov.32 d30[0],
 ; CHECK: vmov q8, q15
   %tmp = alloca %struct.int32x4_t, align 16
   call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind

Modified: llvm/trunk/test/CodeGen/Mips/buildpairextractelementf64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/buildpairextractelementf64.ll?rev=129739&r1=129738&r2=129739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/buildpairextractelementf64.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/buildpairextractelementf64.ll Mon Apr 18 19:14:43 2011
@@ -1,13 +1,11 @@
-; RUN: llc  < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-EL
-; RUN: llc  < %s -march=mips   | FileCheck %s -check-prefix=CHECK-EB
+; RUN: llc  < %s -march=mipsel | FileCheck %s
+; RUN: llc  < %s -march=mips   | FileCheck %s
 @a = external global i32
 
 define double @f(i32 %a1, double %d) nounwind {
 entry:
-; CHECK-EL: mtc1 $6, $f12
-; CHECK-EL: mtc1 $7, $f13
-; CHECK-EB: mtc1 $7, $f12
-; CHECK-EB: mtc1 $6, $f13
+; CHECK: mtc1
+; CHECK: mtc1
   store i32 %a1, i32* @a, align 4
   %add = fadd double %d, 2.000000e+00
   ret double %add
@@ -15,10 +13,8 @@
 
 define void @f3(double %d, i32 %a1) nounwind {
 entry:
-; CHECK-EL: mfc1 ${{[0-9]+}}, $f12
-; CHECK-EL: mfc1 $7, $f13
-; CHECK-EB: mfc1 ${{[0-9]+}}, $f13
-; CHECK-EB: mfc1 $7, $f12
+; CHECK: mfc1
+; CHECK: mfc1
   tail call void @f2(i32 %a1, double %d) nounwind
   ret void
 }

Modified: llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll?rev=129739&r1=129738&r2=129739&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll Mon Apr 18 19:14:43 2011
@@ -10,7 +10,7 @@
 define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind {
 ; CHECK: blx ___muldf3
 ; CHECK: blx ___muldf3
-; CHECK: beq LBB0_7
+; CHECK: beq LBB0
 ; CHECK: blx ___muldf3
 ; <label>:3
   switch i32 %1, label %4 [