[llvm-commits] [llvm] r129711 - in /llvm/trunk: lib/CodeGen/RegAllocFast.cpp test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll

[Eric Christopher]

Author: echristo
Date: Mon Apr 18 14:26:25 2011
New Revision: 129711

URL: http://llvm.org/viewvc/llvm-project?rev=129711&view=rev
Log:
Fix a bug where we were counting the alias sets as completely used
registers for fast allocation a different way. This has us updating
used registers only when we're using that exact register.

Fixes rdar://9207598


Added:
    llvm/trunk/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
Modified:
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=129711&r1=129710&r2=129711&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Mon Apr 18 14:26:25 2011
@@ -396,7 +396,6 @@
   PhysRegState[PhysReg] = NewState;
   for (const unsigned *AS = TRI->getAliasSet(PhysReg);
        unsigned Alias = *AS; ++AS) {
-    UsedInInstr.set(Alias);
     switch (unsigned VirtReg = PhysRegState[Alias]) {
     case regDisabled:
       break;
@@ -734,10 +733,6 @@
     if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
     DEBUG(dbgs() << "\tSetting reg " << Reg << " as used in instr\n");
     UsedInInstr.set(Reg);
-    for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
-      DEBUG(dbgs() << "\tSetting alias reg " << *AS << " as used in instr\n");
-      UsedInInstr.set(*AS);
-    }
   }
 
   // Also mark PartialDefs as used to avoid reallocation.

Added: llvm/trunk/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll?rev=129711&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll Mon Apr 18 14:26:25 2011
@@ -0,0 +1,15 @@
+; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast
+; Previously we'd crash as out of registers on this input by clobbering all of
+; the aliases.
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
+target triple = "thumbv7-apple-darwin10.0.0"
+
+define void @_Z8TestCasev() nounwind ssp {
+entry:
+  %a = alloca float, align 4
+  %tmp = load float* %a, align 4
+  call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0
+  ret void
+}
+
+!0 = metadata !{i32 109}