[llvm-commits] [llvm] r129610 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll

[Cameron Zwarich]

Author: zwarich
Date: Fri Apr 15 16:24:38 2011
New Revision: 129610

URL: http://llvm.org/viewvc/llvm-project?rev=129610&view=rev
Log:
Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate
a case involving EOR, so I only added a test for ORR.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=129610&r1=129609&r2=129610&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Apr 15 16:24:38 2011
@@ -1642,7 +1642,15 @@
   case ARM::ANDrr:
   case ARM::ANDri:
   case ARM::t2ANDrr:
-  case ARM::t2ANDri: {
+  case ARM::t2ANDri:
+  case ARM::ORRrr:
+  case ARM::ORRri:
+  case ARM::t2ORRrr:
+  case ARM::t2ORRri:
+  case ARM::EORrr:
+  case ARM::EORri:
+  case ARM::t2EORrr:
+  case ARM::t2EORri: {
     // Scan forward for the use of CPSR, if it's a conditional code requires
     // checking of V bit, then this is not safe to do. If we can't find the
     // CPSR use (i.e. used in another block), then it's not safe to perform

Modified: llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll?rev=129610&r1=129609&r2=129610&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll Fri Apr 15 16:24:38 2011
@@ -3,7 +3,7 @@
 ; CHECK: _f
 ; CHECK: adds
 ; CHECK-NOT: cmp
-; CHECK: blxeq _g
+; CHECK: blxeq _h
 
 define i32 @f(i32 %a, i32 %b) nounwind ssp {
 entry:
@@ -12,11 +12,30 @@
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
-  tail call void (...)* @g(i32 %a, i32 %b) nounwind
+  tail call void (...)* @h(i32 %a, i32 %b) nounwind
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret i32 %add
 }
 
-declare void @g(...)
+; CHECK: _g
+; CHECK: orrs
+; CHECK-NOT: cmp
+; CHECK: blxeq _h
+
+define i32 @g(i32 %a, i32 %b) nounwind ssp {
+entry:
+  %add = or i32 %b, %a
+  %cmp = icmp eq i32 %add, 0
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  tail call void (...)* @h(i32 %a, i32 %b) nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %add
+}
+
+declare void @h(...)