[llvm-commits] [llvm] r129599 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
Cameron Zwarich
zwarich at apple.com
Fri Apr 15 13:28:29 PDT 2011
Author: zwarich
Date: Fri Apr 15 15:28:28 2011
New Revision: 129599
URL: http://llvm.org/viewvc/llvm-project?rev=129599&view=rev
Log:
Add missing register forms of instructions to the ARM CMP-folding code. This
fixes <rdar://problem/9287901>.
Added:
llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=129599&r1=129598&r2=129599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Apr 15 15:28:28 2011
@@ -1618,16 +1618,26 @@
// Set the "zero" bit in CPSR.
switch (MI->getOpcode()) {
default: break;
+ case ARM::RSBrr:
case ARM::RSBri:
+ case ARM::RSCrr:
case ARM::RSCri:
+ case ARM::ADDrr:
case ARM::ADDri:
+ case ARM::ADCrr:
case ARM::ADCri:
+ case ARM::SUBrr:
case ARM::SUBri:
+ case ARM::SBCrr:
case ARM::SBCri:
case ARM::t2RSBri:
+ case ARM::t2ADDrr:
case ARM::t2ADDri:
+ case ARM::t2ADCrr:
case ARM::t2ADCri:
+ case ARM::t2SUBrr:
case ARM::t2SUBri:
+ case ARM::t2SBCrr:
case ARM::t2SBCri: {
// Scan forward for the use of CPSR, if it's a conditional code requires
// checking of V bit, then this is not safe to do. If we can't find the
@@ -1669,7 +1679,9 @@
// fallthrough
}
+ case ARM::ANDrr:
case ARM::ANDri:
+ case ARM::t2ANDrr:
case ARM::t2ANDri:
// Toggle the optional operand to CPSR.
MI->getOperand(5).setReg(ARM::CPSR);
Added: llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll?rev=129599&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll Fri Apr 15 15:28:28 2011
@@ -0,0 +1,22 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
+
+; CHECK: _f
+; CHECK: adds
+; CHECK-NOT: cmp
+; CHECK: blxeq _g
+
+define i32 @f(i32 %a, i32 %b) nounwind ssp {
+entry:
+ %add = add nsw i32 %b, %a
+ %cmp = icmp eq i32 %add, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void (...)* @g(i32 %a, i32 %b) nounwind
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret i32 %add
+}
+
+declare void @g(...)
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