[llvm-commits] [llvm] r129498 - in /llvm/trunk: lib/Target/X86/ test/CodeGen/X86/ test/MC/X86/
Bill Wendling
isanbard at gmail.com
Wed Apr 13 18:46:37 PDT 2011
Author: void
Date: Wed Apr 13 20:46:37 2011
New Revision: 129498
URL: http://llvm.org/viewvc/llvm-project?rev=129498&view=rev
Log:
As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
(movzx/movsx) because they give more information. Revert that part of the patch.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll
llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
llvm/trunk/test/CodeGen/X86/anyext.ll
llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
llvm/trunk/test/CodeGen/X86/bool-zext.ll
llvm/trunk/test/CodeGen/X86/cmov.ll
llvm/trunk/test/CodeGen/X86/cmp.ll
llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll
llvm/trunk/test/CodeGen/X86/h-registers-0.ll
llvm/trunk/test/CodeGen/X86/h-registers-2.ll
llvm/trunk/test/CodeGen/X86/inline-asm-mrv.ll
llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll
llvm/trunk/test/CodeGen/X86/pr3366.ll
llvm/trunk/test/CodeGen/X86/promote-assert-zext.ll
llvm/trunk/test/CodeGen/X86/promote-i16.ll
llvm/trunk/test/CodeGen/X86/select.ll
llvm/trunk/test/CodeGen/X86/setcc.ll
llvm/trunk/test/CodeGen/X86/sext-ret-val.ll
llvm/trunk/test/CodeGen/X86/sext-subreg.ll
llvm/trunk/test/CodeGen/X86/shl_elim.ll
llvm/trunk/test/CodeGen/X86/umul-with-overflow.ll
llvm/trunk/test/CodeGen/X86/vshift-4.ll
llvm/trunk/test/CodeGen/X86/widen_conv-2.ll
llvm/trunk/test/CodeGen/X86/x86-64-shortint.ll
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Apr 13 20:46:37 2011
@@ -1546,21 +1546,21 @@
def : InstAlias<"movsd", (MOVSD)>;
// movsx aliases
-def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src)>;
-def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)>;
-def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src)>;
-def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src)>;
-def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src)>;
-def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src)>;
-def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src)>;
+def : InstAlias<"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8:$src), 0>;
+def : InstAlias<"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src), 0>;
+def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
+def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
+def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
// movzx aliases
-def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src)>;
-def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src)>;
-def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src)>;
-def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src)>;
-def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src)>;
-def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src)>;
+def : InstAlias<"movzx $src, $dst", (MOVZX16rr8W GR16:$dst, GR8:$src), 0>;
+def : InstAlias<"movzx $src, $dst", (MOVZX16rm8W GR16:$dst, i8mem:$src), 0>;
+def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
+def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
+def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
+def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
// Note: No GR32->GR64 movzx form.
// outb %dx -> outb %al, %dx
Modified: llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2006-11-17-IllegalMove.ll Wed Apr 13 20:46:37 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86-64 > %t
; RUN: grep movb %t | count 2
-; RUN: grep {movzx} %t
+; RUN: grep {movzb\[wl\]} %t
define void @handle_vector_size_attribute() nounwind {
Modified: llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll Wed Apr 13 20:46:37 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep {movsx}
+; RUN: llc < %s -march=x86 | grep {movsbl}
@X = global i32 0 ; <i32*> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll Wed Apr 13 20:46:37 2011
@@ -1,10 +1,9 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movzbl
define i32 @foo(<4 x float> %a, <4 x float> %b) nounwind {
entry:
-; CHECK: movzx
- tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
- ret i32 %0
+ tail call i32 @llvm.x86.sse.ucomige.ss( <4 x float> %a, <4 x float> %b ) nounwind readnone
+ ret i32 %0
}
declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>) nounwind readnone
Modified: llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-06-05-VZextByteShort.ll Wed Apr 13 20:46:37 2011
@@ -1,8 +1,9 @@
-; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 > %t1
+; RUN: grep movzwl %t1 | count 2
+; RUN: grep movzbl %t1 | count 2
+; RUN: grep movd %t1 | count 4
define <4 x i16> @a(i32* %x1) nounwind {
-; CHECK: movzx
-; CHECK-NEXT: movd
%x2 = load i32* %x1
%x3 = lshr i32 %x2, 1
%x = trunc i32 %x3 to i16
@@ -11,8 +12,6 @@
}
define <8 x i16> @b(i32* %x1) nounwind {
-; CHECK: movzx
-; CHECK-NEXT: movd
%x2 = load i32* %x1
%x3 = lshr i32 %x2, 1
%x = trunc i32 %x3 to i16
@@ -21,8 +20,6 @@
}
define <8 x i8> @c(i32* %x1) nounwind {
-; CHECK: movzx
-; CHECK-NEXT: movd
%x2 = load i32* %x1
%x3 = lshr i32 %x2, 1
%x = trunc i32 %x3 to i8
@@ -31,8 +28,6 @@
}
define <16 x i8> @d(i32* %x1) nounwind {
-; CHECK: movzx
-; CHECK-NEXT: movd
%x2 = load i32* %x1
%x3 = lshr i32 %x2, 1
%x = trunc i32 %x3 to i8
Modified: llvm/trunk/test/CodeGen/X86/anyext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/anyext.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/anyext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/anyext.ll Wed Apr 13 20:46:37 2011
@@ -1,10 +1,8 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | grep movzbl | count 2
-; Use movzbl (aliased as movzx) to avoid partial-register updates.
+; Use movzbl to avoid partial-register updates.
define i32 @foo(i32 %p, i8 zeroext %x) nounwind {
-; CHECK: movzx %dil, %eax
-; CHECK: movzx %al, %eax
%q = trunc i32 %p to i8
%r = udiv i8 %q, %x
%s = zext i8 %r to i32
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-x86.ll Wed Apr 13 20:46:37 2011
@@ -75,7 +75,7 @@
define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vcomisd
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -85,7 +85,7 @@
define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vcomisd
; CHECK: setae
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -95,7 +95,7 @@
define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vcomisd
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -105,7 +105,7 @@
define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vcomisd
; CHECK: setbe
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -125,7 +125,7 @@
define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vcomisd
; CHECK: setne
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -786,7 +786,7 @@
define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vucomisd
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -796,7 +796,7 @@
define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vucomisd
; CHECK: setae
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -806,7 +806,7 @@
define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vucomisd
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -816,7 +816,7 @@
define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vucomisd
; CHECK: setbe
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -835,7 +835,7 @@
define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vucomisd
; CHECK: setne
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1192,7 +1192,7 @@
define i32 @test_x86_sse41_ptestnzc(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vptest
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse41.ptestnzc(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1202,7 +1202,7 @@
define i32 @test_x86_sse41_ptestz(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vptest
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1414,7 +1414,7 @@
define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vcomiss
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1424,7 +1424,7 @@
define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vcomiss
; CHECK: setae
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1434,7 +1434,7 @@
define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vcomiss
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1444,7 +1444,7 @@
define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vcomiss
; CHECK: setbe
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1463,7 +1463,7 @@
define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vcomiss
; CHECK: setne
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1655,7 +1655,7 @@
define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vucomiss
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1665,7 +1665,7 @@
define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vucomiss
; CHECK: setae
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1675,7 +1675,7 @@
define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vucomiss
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1685,7 +1685,7 @@
define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vucomiss
; CHECK: setbe
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -1704,7 +1704,7 @@
define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vucomiss
; CHECK: setne
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2179,7 +2179,7 @@
define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK: vptest
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2189,7 +2189,7 @@
define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK: vptest
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2483,7 +2483,7 @@
define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vtestpd
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2493,7 +2493,7 @@
define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
; CHECK: vtestpd
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2503,7 +2503,7 @@
define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vtestps
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2513,7 +2513,7 @@
define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
; CHECK: vtestps
; CHECK: seta
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2523,7 +2523,7 @@
define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
; CHECK: vtestpd
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2533,7 +2533,7 @@
define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
; CHECK: vtestpd
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2543,7 +2543,7 @@
define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
; CHECK: vtestps
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
@@ -2553,7 +2553,7 @@
define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
; CHECK: vtestps
; CHECK: sete
- ; CHECK: movzx
+ ; CHECK: movzbl
%res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
ret i32 %res
}
Modified: llvm/trunk/test/CodeGen/X86/bool-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bool-zext.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bool-zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bool-zext.ll Wed Apr 13 20:46:37 2011
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86-64 | FileCheck %s
; CHECK: @bar1
-; CHECK: movzx
+; CHECK: movzbl
; CHECK: callq
define void @bar1(i1 zeroext %v1) nounwind ssp {
entry:
@@ -11,7 +11,7 @@
}
; CHECK: @bar2
-; CHECK-NOT: movzx
+; CHECK-NOT: movzbl
; CHECK: callq
define void @bar2(i8 zeroext %v1) nounwind ssp {
entry:
@@ -22,7 +22,7 @@
; CHECK: @bar3
; CHECK: callq
-; CHECK-NOT: movzx
+; CHECK-NOT: movzbl
; CHECK-NOT: and
; CHECK: ret
define zeroext i1 @bar3() nounwind ssp {
Modified: llvm/trunk/test/CodeGen/X86/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov.ll Wed Apr 13 20:46:37 2011
@@ -121,7 +121,7 @@
entry:
; CHECK: test5:
; CHECK: setg %al
-; CHECK: movzx %al, %eax
+; CHECK: movzbl %al, %eax
; CHECK: orl $-2, %eax
; CHECK: ret
@@ -135,7 +135,7 @@
entry:
; CHECK: test6:
; CHECK: setl %al
-; CHECK: movzx %al, %eax
+; CHECK: movzbl %al, %eax
; CHECK: leal 4(%rax,%rax,8), %eax
; CHECK: ret
%0 = load i32* %P, align 4 ; <i32> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmp.ll Wed Apr 13 20:46:37 2011
@@ -38,7 +38,7 @@
; CHECK: test3:
; CHECK: testq %rdi, %rdi
; CHECK: sete %al
-; CHECK: movzx %al, %eax
+; CHECK: movzbl %al, %eax
; CHECK: ret
}
@@ -49,7 +49,7 @@
; CHECK: test4:
; CHECK: testq %rdi, %rdi
; CHECK: setle %al
-; CHECK: movzx %al, %eax
+; CHECK: movzbl %al, %eax
; CHECK: ret
}
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Wed Apr 13 20:46:37 2011
@@ -14,7 +14,7 @@
; X32: ret
; X64: test1:
-; X64: movsx %e[[A0:di|cx]], %rax
+; X64: movslq %e[[A0:di|cx]], %rax
; X64: movl (%r[[A1:si|dx]],%rax,4), %eax
; X64: ret
@@ -81,7 +81,7 @@
%v11 = add i64 %B, %v10
ret i64 %v11
; X64: test5:
-; X64: movsx %e[[A1]], %rax
+; X64: movslq %e[[A1]], %rax
; X64-NEXT: movq (%r[[A0]],%rax), %rax
; X64-NEXT: addq %{{rdx|r8}}, %rax
; X64-NEXT: ret
Modified: llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-register-addressing-32.ll Wed Apr 13 20:46:37 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep {movzx %\[abcd\]h,} | count 7
+; RUN: llc < %s -march=x86 | grep {movzbl %\[abcd\]h,} | count 7
; Use h-register extract and zero-extend.
Modified: llvm/trunk/test/CodeGen/X86/h-registers-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-0.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-registers-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-registers-0.ll Wed Apr 13 20:46:37 2011
@@ -70,7 +70,7 @@
; WIN64: movzbl %ch, %eax
; X86-32: qux64:
-; X86-32: movzx %ah, %eax
+; X86-32: movzbl %ah, %eax
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
ret i64 %t1
@@ -85,7 +85,7 @@
; WIN64: movzbl %ch, %eax
; X86-32: qux32:
-; X86-32: movzx %ah, %eax
+; X86-32: movzbl %ah, %eax
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
ret i32 %t1
@@ -100,7 +100,7 @@
; WIN64: movzbl %ch, %eax
; X86-32: qux16:
-; X86-32: movzx %ah, %eax
+; X86-32: movzbl %ah, %eax
%t0 = lshr i16 %x, 8
ret i16 %t0
}
Modified: llvm/trunk/test/CodeGen/X86/h-registers-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/h-registers-2.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/h-registers-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/h-registers-2.ll Wed Apr 13 20:46:37 2011
@@ -1,5 +1,5 @@
; RUN: llc < %s -march=x86 > %t
-; RUN: grep {movzx %\[abcd\]h,} %t | count 1
+; RUN: grep {movzbl %\[abcd\]h,} %t | count 1
; RUN: grep {shll \$3,} %t | count 1
; Use an h register, but don't omit the explicit shift for
Modified: llvm/trunk/test/CodeGen/X86/inline-asm-mrv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-mrv.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/inline-asm-mrv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/inline-asm-mrv.ll Wed Apr 13 20:46:37 2011
@@ -1,5 +1,5 @@
; PR2094
-; RUN: llc < %s -march=x86-64 | grep movsx
+; RUN: llc < %s -march=x86-64 | grep movslq
; RUN: llc < %s -march=x86-64 | grep addps
; RUN: llc < %s -march=x86-64 | grep paddd
; RUN: llc < %s -march=x86-64 | not grep movq
Modified: llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll (original)
+++ llvm/trunk/test/CodeGen/X86/masked-iv-unsafe.ll Wed Apr 13 20:46:37 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86-64 > %t
; RUN: grep and %t | count 6
-; RUN: grep movzx %t | count 6
+; RUN: grep movzb %t | count 6
; RUN: grep sar %t | count 12
; Don't optimize away zext-inreg and sext-inreg on the loop induction
Modified: llvm/trunk/test/CodeGen/X86/pr3366.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3366.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr3366.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr3366.ll Wed Apr 13 20:46:37 2011
@@ -1,7 +1,6 @@
-; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s
+; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl
; PR3366
-; CHECK: movzx
define void @_ada_c34002a() nounwind {
entry:
%0 = load i8* null, align 1
Modified: llvm/trunk/test/CodeGen/X86/promote-assert-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/promote-assert-zext.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/promote-assert-zext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/promote-assert-zext.ll Wed Apr 13 20:46:37 2011
@@ -7,7 +7,7 @@
; ISel doesn't yet know how to eliminate this extra zero-extend. But until
; it knows how to do so safely, it shouldn;t eliminate it.
; CHECK: movzbl (%rdi), %eax
-; CHECK: movzx %ax, %eax
+; CHECK: movzwl %ax, %eax
define i64 @_ZL5matchPKtPKhiR9MatchData(i8* %tmp13) nounwind {
entry:
Modified: llvm/trunk/test/CodeGen/X86/promote-i16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/promote-i16.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/promote-i16.ll (original)
+++ llvm/trunk/test/CodeGen/X86/promote-i16.ll Wed Apr 13 20:46:37 2011
@@ -4,8 +4,8 @@
entry:
; CHECK: foo:
; CHECK: movzwl 4(%esp), %eax
-; CHECK: xorl $21998, %eax
-; CHECK: movsx %ax, %eax
+; CHECK: xorl $21998, %eax
+; CHECK: movswl %ax, %eax
%0 = xor i16 %x, 21998
ret i16 %0
}
Modified: llvm/trunk/test/CodeGen/X86/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/select.ll (original)
+++ llvm/trunk/test/CodeGen/X86/select.ll Wed Apr 13 20:46:37 2011
@@ -30,7 +30,7 @@
ret i32 0
; CHECK: test2:
; CHECK: movnew
-; CHECK: movsx
+; CHECK: movswl
}
declare i1 @return_false()
Modified: llvm/trunk/test/CodeGen/X86/setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setcc.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/setcc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/setcc.ll Wed Apr 13 20:46:37 2011
@@ -8,7 +8,7 @@
entry:
; CHECK: t1:
; CHECK: seta %al
-; CHECK: movzx %al, %eax
+; CHECK: movzbl %al, %eax
; CHECK: shll $5, %eax
%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/sext-ret-val.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-ret-val.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sext-ret-val.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sext-ret-val.ll Wed Apr 13 20:46:37 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep movzx | count 1
+; RUN: llc < %s -march=x86 | grep movzbl | count 1
; rdar://6699246
define signext i8 @t1(i8* %A) nounwind readnone ssp {
Modified: llvm/trunk/test/CodeGen/X86/sext-subreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sext-subreg.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sext-subreg.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sext-subreg.ll Wed Apr 13 20:46:37 2011
@@ -3,7 +3,7 @@
define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
; CHECK: t:
-; CHECK: movsx %e{{.*}}, %rax
+; CHECK: movslq %e{{.*}}, %rax
; CHECK: movq %rax
; CHECK: movl %eax
%C = add i64 %A, %B
Modified: llvm/trunk/test/CodeGen/X86/shl_elim.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shl_elim.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shl_elim.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shl_elim.ll Wed Apr 13 20:46:37 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 | grep {movl 8(.esp), %eax}
; RUN: llc < %s -march=x86 | grep {shrl .eax}
-; RUN: llc < %s -march=x86 | grep {movsx .ax, .eax}
+; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax}
define i32 @test1(i64 %a) nounwind {
%tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/umul-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/umul-with-overflow.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/umul-with-overflow.ll (original)
+++ llvm/trunk/test/CodeGen/X86/umul-with-overflow.ll Wed Apr 13 20:46:37 2011
@@ -9,6 +9,6 @@
; CHECK: a:
; CHECK: mull
; CHECK: seto %al
-; CHECK: movzx %al, %eax
+; CHECK: movzbl %al, %eax
; CHECK: ret
}
Modified: llvm/trunk/test/CodeGen/X86/vshift-4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vshift-4.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vshift-4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vshift-4.ll Wed Apr 13 20:46:37 2011
@@ -57,7 +57,7 @@
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
entry:
; CHECK: shift3a:
-; CHECK: movzx
+; CHECK: movzwl
; CHECK: psllw
%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
%shl = shl <8 x i16> %val, %shamt
Modified: llvm/trunk/test/CodeGen/X86/widen_conv-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_conv-2.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_conv-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_conv-2.ll Wed Apr 13 20:46:37 2011
@@ -1,6 +1,6 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
-; CHECK: movsx
-; CHECK: movsx
+; CHECK: movswl
+; CHECK: movswl
; sign extension v2i32 to v2i16
Modified: llvm/trunk/test/CodeGen/X86/x86-64-shortint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-64-shortint.ll?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-64-shortint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-64-shortint.ll Wed Apr 13 20:46:37 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s | grep movsx
+; RUN: llc < %s | grep movswl
target datalayout = "e-p:64:64"
target triple = "x86_64-apple-darwin8"
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=129498&r1=129497&r2=129498&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Wed Apr 13 20:46:37 2011
@@ -681,65 +681,65 @@
// CHECK: encoding: [0x48,0x0f,0xba,0xe2,0x01]
//rdar://8017633
-// CHECK: movzx %al, %esi
+// CHECK: movzbl %al, %esi
// CHECK: encoding: [0x0f,0xb6,0xf0]
movzx %al, %esi
-// CHECK: movzx %al, %rsi
+// CHECK: movzbq %al, %rsi
// CHECK: encoding: [0x48,0x0f,0xb6,0xf0]
movzx %al, %rsi
-// CHECK: movsx %al, %ax
+// CHECK: movsbw %al, %ax
// CHECK: encoding: [0x66,0x0f,0xbe,0xc0]
- movsx %al, %ax
+movsx %al, %ax
-// CHECK: movsx %al, %eax
+// CHECK: movsbl %al, %eax
// CHECK: encoding: [0x0f,0xbe,0xc0]
- movsx %al, %eax
+movsx %al, %eax
-// CHECK: movsx %ax, %eax
+// CHECK: movswl %ax, %eax
// CHECK: encoding: [0x0f,0xbf,0xc0]
- movsx %ax, %eax
+movsx %ax, %eax
-// CHECK: movsx %bl, %rax
+// CHECK: movsbq %bl, %rax
// CHECK: encoding: [0x48,0x0f,0xbe,0xc3]
- movsx %bl, %rax
+movsx %bl, %rax
-// CHECK: movsx %cx, %rax
+// CHECK: movswq %cx, %rax
// CHECK: encoding: [0x48,0x0f,0xbf,0xc1]
- movsx %cx, %rax
+movsx %cx, %rax
-// CHECK: movsx %edi, %rax
+// CHECK: movslq %edi, %rax
// CHECK: encoding: [0x48,0x63,0xc7]
- movsx %edi, %rax
+movsx %edi, %rax
-// CHECK: movzx %al, %ax
+// CHECK: movzbw %al, %ax
// CHECK: encoding: [0x66,0x0f,0xb6,0xc0]
- movzx %al, %ax
+movzx %al, %ax
-// CHECK: movzx %al, %eax
+// CHECK: movzbl %al, %eax
// CHECK: encoding: [0x0f,0xb6,0xc0]
- movzx %al, %eax
+movzx %al, %eax
-// CHECK: movzx %ax, %eax
+// CHECK: movzwl %ax, %eax
// CHECK: encoding: [0x0f,0xb7,0xc0]
- movzx %ax, %eax
+movzx %ax, %eax
-// CHECK: movzx %bl, %rax
+// CHECK: movzbq %bl, %rax
// CHECK: encoding: [0x48,0x0f,0xb6,0xc3]
- movzx %bl, %rax
+movzx %bl, %rax
-// CHECK: movzx %cx, %rax
+// CHECK: movzwq %cx, %rax
// CHECK: encoding: [0x48,0x0f,0xb7,0xc1]
- movzx %cx, %rax
+movzx %cx, %rax
// CHECK: movsbw (%rax), %ax
// CHECK: encoding: [0x66,0x0f,0xbe,0x00]
- movsx (%rax), %ax
+movsx (%rax), %ax
// CHECK: movzbw (%rax), %ax
// CHECK: encoding: [0x66,0x0f,0xb6,0x00]
- movzx (%rax), %ax
+movzx (%rax), %ax
// rdar://7873482
More information about the llvm-commits
mailing list