[llvm-commits] [llvm] r129469 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt

[Johnny Chen]

Author: johnny
Date: Wed Apr 13 16:04:32 2011
New Revision: 129469

URL: http://llvm.org/viewvc/llvm-project?rev=129469&view=rev
Log:
The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.

rdar://problem/9279440

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=129469&r1=129468&r2=129469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Apr 13 16:04:32 2011
@@ -1381,7 +1381,7 @@
 // for disassembly only.
 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
-  : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
+  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
           "\t$Rt, $addr", []> {
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;
@@ -1472,7 +1472,7 @@
 // only.
 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
-  : T2Ii8<(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
+  : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc,
           "\t$Rt, $addr", []> {
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=129469&r1=129468&r2=129469&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed Apr 13 16:04:32 2011
@@ -1909,6 +1909,8 @@
   // Inst{22-21} encodes the data item transferred for load/store.
   // For single word, it is encoded as ob10.
   bool Word = (slice(insn, 22, 21) == 2);
+  bool Half = (slice(insn, 22, 21) == 1);
+  bool Byte = (slice(insn, 22, 21) == 0);
 
   if (UseRm && BadReg(R2)) {
     DEBUG(errs() << "if BadReg(m) then UNPREDICTABLE\n");
@@ -1920,9 +1922,15 @@
       DEBUG(errs() << "if t == 13 then UNPREDICTABLE\n");
       return true;
     }
+    if (Byte) {
+      if (WB && R0 == 15 && slice(insn, 10, 8) == 3)  {
+        // A8.6.78 LDRSB (immediate) Encoding T2 (errata markup 8.0)
+        DEBUG(errs() << "if t == 15 && PUW == '011' then UNPREDICTABLE\n");
+        return true;
+      }
+    }
     // A6.3.8 Load halfword, memory hints
-    const StringRef Name = ARMInsts[Opcode].Name;
-    if (Name.startswith("t2LDRH") || Name.startswith("t2LDRSH")) {
+    if (Half) {
       if (WB) {
         if (R0 == R1)  {
           // A8.6.82 LDRSH (immediate) Encoding T2
@@ -2021,8 +2029,8 @@
   OpIdx = 0;
 
   assert(NumOps >= 3 &&
-         OpInfo[0].RegClass == ARM::GPRRegClassID &&
-         OpInfo[1].RegClass == ARM::GPRRegClassID &&
+         OpInfo[0].RegClass > 0 &&
+         OpInfo[1].RegClass > 0 &&
          "Expect >= 3 operands and first two as reg operands");
 
   bool ThreeReg = (OpInfo[2].RegClass > 0);
@@ -2061,10 +2069,10 @@
       Imm = decodeImm8(insn);
   }
 
-  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
                                                      R0)));
   ++OpIdx;
-  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+  MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
                                                      R1)));
   ++OpIdx;
 

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt?rev=129469&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt Wed Apr 13 16:04:32 2011
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# 
+# The unpriviledged Load/Store cannot have SP or PC as Rt.
+0x10 0xf8 0x3 0xfe