[llvm-commits] Source register same as write-back base

[Joe Abbey]

-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: Monday, April 11, 2011 7:44 PM
To: Johnny Chen
Cc: Joe Abbey; Commit Messages and Patches for LLVM
Subject: Re: [llvm-commits] Source register same as write-back base


On Apr 11, 2011, at 2:27 PM, Johnny Chen wrote:

> Hi Joe,
> 
> I've CCed llvm-commit.  Hopefully the backend folks can help you out!
> Thanks.
> 
> On Apr 11, 2011, at 2:20 PM, Joe Abbey wrote:
> 
>> Johnny,
>>  
>> I saw your changelist which adds a check to the disassembly of ARM
instructions.
>>  
>> I'm currently trying to debug how the register allocation works to
produce:
>>  
>> str r3, [r3], #4
>>  
>> My assembler is complaining that:
>>  
>> libtest-libstl.so.bc:46025: Warning: source register same as
write-back base
>>  
>> And it should because as you (and ARM) note, this is UNPREDICTABLE.

Is this the same situation as the armV5 MUL instructions where the
documents say it is unpredictable, but all existing hardware
implementations behave correctly?

Which architecture revisions have this constraint?

/jakob


Jakob,

Yes this is the same restriction as armV5 MUL, and it is likely the case
that all hardware implementations behave correctly.  

However, this restriction is documented in ARMv5 & ARMv7:

DD101001 A4.1.99
If <addressing_mode> specifies base register write-back, and the same
register is specified for <Rd> and <Rn>, the results are UNPREDICTABLE.

DDI0406B A8.6.194
if wback && (n == 15 || n == t) then UNPREDICTABLE;

I see that in ARMInstrInfo.td MULv5 considers $Rd to be earlyclobber.  

Could a similar pattern of making $Rt earlyclobber be applied in the
store instrucitons? 

Cheers,

Joe