[llvm-commits] [llvm] r129098 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt test/MC/Disassembler/ARM/invalid-SXTB-arm.txt

Johnny Chen johnny.chen at apple.com
Thu Apr 7 12:28:59 PDT 2011


Author: johnny
Date: Thu Apr  7 14:28:58 2011
New Revision: 129098

URL: http://llvm.org/viewvc/llvm-project?rev=129098&view=rev
Log:
Add sanity checking for invalid register encodings for signed/unsigned extend instructions.
Add some test cases.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=129098&r1=129097&r2=129098&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Thu Apr  7 14:28:58 2011
@@ -1589,6 +1589,11 @@
 static bool DisassembleExtFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
     unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
 
+  // A8.6.220 SXTAB
+  // if d == 15 || m == 15 then UNPREDICTABLE;
+  if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
+    return false;
+
   const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
   unsigned &OpIdx = NumOpsAdded;
 

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=129098&r1=129097&r2=129098&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Apr  7 14:28:58 2011
@@ -248,3 +248,9 @@
 
 # CHECK:	lsl	r3, r2, r1
 0x12 0x31 0xa0 0xe1
+
+# CHECK:	sxtab	r9, r8, r5
+0x75 0x90 0xa8 0xe6
+
+# CHECK:	sxtb	r9, r5, ror #8
+0x75 0x94 0xaf 0xe6

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt?rev=129098&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt Thu Apr  7 14:28:58 2011
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.223 SXTB
+# if d == 15 || m == 15 then UNPREDICTABLE;
+0x75 0xf4 0xaf 0xe6





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