[llvm-commits] [llvm] r129090 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt test/MC/Disassembler/ARM/invalid-LSL-regform.txt

[Johnny Chen]

Author: johnny
Date: Thu Apr  7 13:33:19 2011
New Revision: 129090

URL: http://llvm.org/viewvc/llvm-project?rev=129090&view=rev
Log:
Add some more comments about checkings of invalid register numbers.
And two test cases.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=129090&r1=129089&r2=129090&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Thu Apr  7 13:33:19 2011
@@ -1110,6 +1110,11 @@
 
     // A8.6.3 ADC (register-shifted register)
     // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+    // 
+    // This also accounts for shift instructions (register) where, fortunately,
+    // Inst{19-16} = 0b0000.
+    // A8.6.89 LSL (register)
+    // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
     if (decodeRd(insn) == 15 || decodeRn(insn) == 15 ||
         decodeRm(insn) == 15 || decodeRs(insn) == 15)
       return false;

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=129090&r1=129089&r2=129090&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Apr  7 13:33:19 2011
@@ -245,3 +245,6 @@
 
 # CHECK:	smlsldx	r4, r12, r11, r4
 0x7b 0x44 0x4c 0xe7
+
+# CHECK:	lsl	r3, r2, r1
+0x12 0x31 0xa0 0xe1

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt?rev=129090&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LSL-regform.txt Thu Apr  7 13:33:19 2011
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.89 LSL (register)
+# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+0x12 0xf1 0xa0 0xe1