[llvm-commits] [llvm] r129038 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/sub.ll

[Owen Anderson]

Author: resistor
Date: Wed Apr  6 18:35:59 2011
New Revision: 129038

URL: http://llvm.org/viewvc/llvm-project?rev=129038&view=rev
Log:
Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/test/CodeGen/ARM/sub.ll

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=129038&r1=129037&r2=129038&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Apr  6 18:35:59 2011
@@ -1618,10 +1618,17 @@
   // Set the "zero" bit in CPSR.
   switch (MI->getOpcode()) {
   default: break;
+  case ARM::RSBri:
+  case ARM::RSCri:
   case ARM::ADDri:
+  case ARM::ADCri:
   case ARM::SUBri:
+  case ARM::SBCri:
+  case ARM::t2RSBri:
   case ARM::t2ADDri:
-  case ARM::t2SUBri: {
+  case ARM::t2ADCri:
+  case ARM::t2SUBri:
+  case ARM::t2SBCri: {
     // Scan forward for the use of CPSR, if it's a conditional code requires
     // checking of V bit, then this is not safe to do. If we can't find the
     // CPSR use (i.e. used in another block), then it's not safe to perform

Modified: llvm/trunk/test/CodeGen/ARM/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub.ll?rev=129038&r1=129037&r2=129038&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/sub.ll Wed Apr  6 18:35:59 2011
@@ -27,3 +27,12 @@
    ret i64 %tmp
 }
 
+define i32 @f4(i32 %x) {
+entry:
+; CHECK: f4
+; CHECK: rsbs
+  %sub = sub i32 1, %x
+  %cmp = icmp ugt i32 %sub, 0
+  %sel = select i1 %cmp, i32 1, i32 %sub
+  ret i32 %sel
+}