[llvm-commits] [llvm] r128965 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMInstrInfo.td
Jim Grosbach
grosbach at apple.com
Tue Apr 5 17:42:00 PDT 2011
Yay! All around goodness.
A couple of trivial cleanup comments below.
On Apr 5, 2011, at 4:55 PM, Owen Anderson wrote:
> Author: resistor
> Date: Tue Apr 5 18:55:28 2011
> New Revision: 128965
>
> URL: http://llvm.org/viewvc/llvm-project?rev=128965&view=rev
> Log:
> Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128965&r1=128964&r2=128965&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr 5 18:55:28 2011
> @@ -5029,7 +5029,12 @@
> case ARM::ADCSSrs:
> case ARM::SBCSSri:
> case ARM::SBCSSrr:
> - case ARM::SBCSSrs: {
> + case ARM::SBCSSrs:
> + case ARM::RSBSri:
> + case ARM::RSBSrr:
> + case ARM::RSBSrs:
> + case ARM::RSCSri:
> + case ARM::RSCSrs: {
> unsigned OldOpc = MI->getOpcode();
> unsigned Opc = 0;
> switch (OldOpc) {
> @@ -5051,6 +5056,21 @@
> case ARM::SBCSSrs:
> Opc = ARM::SBCrs;
> break;
> + case ARM::RSBSri:
> + Opc = ARM::RSBri;
> + break;
> + case ARM::RSBSrr:
> + Opc = ARM::RSBrr;
> + break;
> + case ARM::RSBSrs:
> + Opc = ARM::RSBrs;
> + break;
> + case ARM::RSCSri:
> + Opc = ARM::RSCri;
> + break;
> + case ARM::RSCSrs:
> + Opc = ARM::RSCrs;
> + break;
> default:
> llvm_unreachable("Unknown opcode?");
> }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128965&r1=128964&r2=128965&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr 5 18:55:28 2011
> @@ -935,7 +935,8 @@
> }
> }
> // Carry setting variants
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> +// NOTE: CPSR def omitted because it will be handled by the custom inserter.
> +let usesCustomInserter = 1 in {
> multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
> def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> Size4Bytes, IIC_iALUi,
> @@ -2243,44 +2244,17 @@
> }
>
> // RSB with 's' bit set.
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> -def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
> - IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
> - [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> imm;
> - let Inst{25} = 1;
> - let Inst{20} = 1;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> - let Inst{11-0} = imm;
> -}
> -def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
> - IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
> - [/* For disassembly only; pattern left blank */]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<4> Rm;
> - let Inst{11-4} = 0b00000000;
> - let Inst{25} = 0;
> - let Inst{20} = 1;
> - let Inst{3-0} = Rm;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> -}
> -def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> - DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
> - [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> shift;
> - let Inst{25} = 0;
> - let Inst{20} = 1;
> - let Inst{11-0} = shift;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> -}
> +// NOTE: CPSR def omitted because it will be handled by the custom inserter.
> +let usesCustomInserter = 1 in {
> +def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> + Size4Bytes, IIC_iALUi,
> + [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
> +def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> + Size4Bytes, IIC_iALUr,
> + [/* For disassembly only; pattern left blank */]>;
> +def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> + Size4Bytes, IIC_iALUsr,
> + [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
> }
>
> let Uses = [CPSR] in {
> @@ -2325,33 +2299,16 @@
> }
>
> // FIXME: Allow these to be predicated.
Can remove this FIXME now, I think. This should do just that, as well as other goodness. :)
> -let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
> -def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> - DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
> +// NOTE: CPSR def omitted because it will be handled by the custom inserter.
> +let usesCustomInserter = 1, Uses = [CPSR] in {
> +def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> + Size4Bytes, IIC_iALUi,
> [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
> - Requires<[IsARM]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> imm;
> - let Inst{25} = 1;
> - let Inst{20} = 1;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> - let Inst{11-0} = imm;
> -}
> -def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> - DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
> + Requires<[IsARM]>;
> +def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> + Size4Bytes, IIC_iALUsr,
> [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
> - Requires<[IsARM]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> shift;
> - let Inst{25} = 0;
> - let Inst{20} = 1;
> - let Inst{11-0} = shift;
> - let Inst{15-12} = Rd;
> - let Inst{19-16} = Rn;
> -}
> + Requires<[IsARM]>;
No need for an explicit "Requires<[IsARM]>" here, as that's already added by the ARMPseudoInst base class.
> }
>
> // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
>
>
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