[llvm-commits] [llvm] r128955 - /llvm/trunk/docs/ReleaseNotes.html

[Chris Lattner]

Author: lattner
Date: Tue Apr  5 18:22:33 2011
New Revision: 128955

URL: http://llvm.org/viewvc/llvm-project?rev=128955&view=rev
Log:
finished my pass through all the 2.9 commits, now to make this intelligible



Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128955&r1=128954&r2=128955&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 18:22:33 2011
@@ -60,18 +60,14 @@
 <a href="http://llvm.org/releases/">releases page</a>.</p>
 
 </div>
-
-<!--
-Almost dead code.
-  lib/Transforms/IPO/MergeFunctions.cpp => consider for 3.0.
--->
- 
    
-<!-- Features that need text if they're finished for 3.0:
+<!-- Features that need text if they're finished for 3.1:
+  ARM EHABI
   combiner-aa?
   strong phi elim
   loop dependence analysis
   CorrelatedValuePropagation
+  lib/Transforms/IPO/MergeFunctions.cpp => consider for 3.1.
  -->
  
 <!-- *********************************************************************** -->
@@ -331,8 +327,9 @@
   
 inline asm multiple alternative constraint support.
   
-LoopIdiom: memset/memcpy formation.  Build with -ffreestanding or -fno-builtin
-  if your memcpy is being compiled into infinite recursion.
+LoopIdiom: memset/memcpy formation and memset_pattern on darwin.  Build with
+  -ffreestanding or -fno-builtin if your memcpy is being compiled into infinite
+  recursion.
   
 
 TargetLibraryInfo
@@ -351,7 +348,7 @@
 
 - DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
   - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
-  For example,
+  For example, DIFactory DebugFactory;
   Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
   findRegion(TYPE_CONTEXT(type)),
   StringRef(),
@@ -364,6 +361,7 @@
   MainTy);
   can be replaced by
   DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy); 
+DIFactory is gone now.
   
 PPC: Switched to MCInstPrinter, and MCCodeEmitter.  Ready to implement support
   for directly writing out mach-o object files, but noone seems interested.
@@ -372,6 +370,9 @@
   
 Scheduler now models operand latency and pipeline forwarding.
   
+Can optimize printf to iprintf when no floating point is used, for embedded
+  targets with smaller iprintf implementation.
+  
 error_code + libsystem + PathV2 changes
   The system_error header from C++0x was added.
   * Use if (error_code ec = function()) to check for error conditions
@@ -407,6 +408,7 @@
   href="CodeGenerator.html#na_instparsing">MnemonicAlias and InstAlias</a>
   
 LoopIndexSplit pass was removed, unmaintained.
+LiveValues, SimplifyHalfPowrLibCalls, and GEPSplitter were removed.
   
 include/llvm/System merged into include/llvm/Support.
  
@@ -460,12 +462,29 @@
 SPARC: Many improvements, including using the Y registers for multiplications
   and addition of a simple delay slot filler.
   
-</pre></li>
-</ul>
   
-Still todo: [110117-110228]
+udiv, ashr, lshr, shl now have exact and nuw/nsw bits: PR8862 / LangRef.html
+  
+lib/Object and llvm-objdump
 
   
+  Target Independent Code Gen:
+  The pre-register-allocation (preRA) instruction scheduler models register pressure
+  much more accurately in some cases. This allows the adoption of more
+  aggressive scheduling heuristics.
+  
+  The X86 backend has adopted a new preRA scheduling
+  mode, "list-ilp", to shorten the height of instruction schedules
+  without inducing register spills.
+  
+  The ARM backend preRA scheduler now models machine resources at cycle
+  granularity. This allows the scheduler to both accurately model
+  instruction latency and avoid overcommitting functional units.
+
+  
+</pre></li>
+</ul>
+  
 </div>
 
 <!--=========================================================================-->