[llvm-commits] [llvm] r128945 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/invalid-RSC-arm.txt

[Johnny Chen]

Author: johnny
Date: Tue Apr  5 17:18:07 2011
New Revision: 128945

URL: http://llvm.org/viewvc/llvm-project?rev=128945&view=rev
Log:
ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.

rdar://problem/9237734

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128945&r1=128944&r2=128945&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 17:18:07 2011
@@ -1072,6 +1072,12 @@
     if (slice(insn, 7, 7))
       return false;
 
+    // A8.6.3 ADC (register-shifted register)
+    // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+    if (decodeRd(insn) == 15 || decodeRn(insn) == 15 ||
+        decodeRm(insn) == 15 || decodeRs(insn) == 15)
+      return false;
+    
     // Register-controlled shifts: [Rm, Rs, shift].
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRs(insn))));

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt?rev=128945&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt Tue Apr  5 17:18:07 2011
@@ -0,0 +1,9 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+0x5f 0xf8 0xe4 0x30