[llvm-commits] [llvm] r128941 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt

[Johnny Chen]

Author: johnny
Date: Tue Apr  5 16:49:44 2011
New Revision: 128941

URL: http://llvm.org/viewvc/llvm-project?rev=128941&view=rev
Log:
ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128941&r1=128940&r2=128941&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 16:49:44 2011
@@ -1068,6 +1068,10 @@
   MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                      decodeRm(insn))));
   if (Rs) {
+    // If Inst{7} != 0, we should reject this insn as an invalid encoding.
+    if (slice(insn, 7, 7))
+      return false;
+
     // Register-controlled shifts: [Rm, Rs, shift].
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRs(insn))));

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt?rev=128941&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt Tue Apr  5 16:49:44 2011
@@ -0,0 +1,9 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# A8.6.89 LSL (register): Inst{7-4} = 0b0001
+0x93 0x42 0xa0 0xd1