[llvm-commits] [llvm] r128936 - in /llvm/trunk/test/CodeGen: ARM/2009-10-27-double-align.ll ARM/arm-returnaddr.ll Mips/2008-08-06-Alloca.ll PowerPC/2010-05-03-retaddr1.ll SPARC/2011-01-11-FrameAddr.ll

Tue Apr 5 14:40:41 PDT 2011

Author: stoklund
Date: Tue Apr  5 16:40:41 2011
New Revision: 128936

URL: http://llvm.org/viewvc/llvm-project?rev=128936&view=rev
Log:
These tests no longer require linear scan because reserved register coalescing is now universal.

Modified:
    llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll
    llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll
    llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll
    llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
    llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll

Modified: llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================

--- llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll Tue Apr  5 16:40:41 2011
@@ -1,6 +1,5 @@
-; RUN: llc < %s  -mtriple=arm-linux-gnueabi -regalloc=linearscan | FileCheck %s
-
-; This test depends on linear scan's reserved register coalescing.
+; RUN: llc < %s  -mtriple=arm-linux-gnueabi | FileCheck %s
+; RUN: llc < %s  -mtriple=arm-linux-gnueabi -regalloc=basic | FileCheck %s
 
 @.str = private constant [1 x i8] zeroinitializer, align 1
 

Modified: llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll Tue Apr  5 16:40:41 2011
@@ -1,11 +1,10 @@
-; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=linearscan | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
 ; rdar://8015977
 ; rdar://8020118
 
-; This test needs the reserved register r7 to be coalesced into the ldr.
-; So far, only linear scan can do that.
-
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
 ; CHECK: rt0:

Modified: llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll Tue Apr  5 16:40:41 2011
@@ -1,9 +1,5 @@
-; RUN: llc < %s -march=mips -regalloc=linearscan | grep {subu.*sp} | count 2
-
-; This test depends on a linearscan optimization, joining copies from reserved
-; registers.
-; After coalescing, copies from %SP remain.
-; They are handled by RALinScan::attemptTrivialCoalescing
+; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
+; RUN: llc < %s -march=mips -regalloc=basic | grep {subu.*sp} | count 2
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll Tue Apr  5 16:40:41 2011
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=linearscan | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=basic | FileCheck %s
 
 declare i8* @llvm.frameaddress(i32) nounwind readnone
 

Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll Tue Apr  5 16:40:41 2011
@@ -1,7 +1,7 @@
-;RUN: llc -march=sparc -regalloc=linearscan < %s | FileCheck %s -check-prefix=V8
-;RUN: llc -march=sparc -regalloc=linearscan -mattr=v9 < %s | FileCheck %s -check-prefix=V9
-
-; These tests depend on linear scan's trivial coalescer for reserved registers.
+;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
+;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
+;RUN: llc -march=sparc -regalloc=basic < %s | FileCheck %s -check-prefix=V8
+;RUN: llc -march=sparc -regalloc=basic -mattr=v9 < %s | FileCheck %s -check-prefix=V9
 
 define i8* @frameaddr() nounwind readnone {
 entry:



