[llvm-commits] [llvm] r128913 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/thumb-printf.txt test/MC/Disassembler/ARM/thumb-tests.txt
Johnny Chen
johnny.chen at apple.com
Tue Apr 5 12:42:11 PDT 2011
Author: johnny
Date: Tue Apr 5 14:42:11 2011
New Revision: 128913
URL: http://llvm.org/viewvc/llvm-project?rev=128913&view=rev
Log:
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128913&r1=128912&r2=128913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr 5 14:42:11 2011
@@ -82,8 +82,16 @@
// FIXME: Auto-gened?
static unsigned
getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
- // For this purpose, we can treat rGPR as if it were GPR.
- if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
+ if (RegClassID == ARM::rGPRRegClassID) {
+ // Check for The register numbers 13 and 15 that are not permitted for many
+ // Thumb register specifiers.
+ if (RawRegister == 13 || RawRegister == 15) {
+ B->SetErr(-1);
+ return 0;
+ }
+ // For this purpose, we can treat rGPR as if it were GPR.
+ RegClassID = ARM::GPRRegClassID;
+ }
// See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
unsigned RegNum =
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt?rev=128913&r1=128912&r2=128913&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt Tue Apr 5 14:42:11 2011
@@ -26,7 +26,8 @@
# CHECK-NEXT: mov r2, r5
# CHECK-NEXT: ldr r3, [sp]
# CHECK-NEXT: bl #-8390
-# CHECK-NEXT: sub.w sp, r7, #8
+# Data bytes (corresponds to an invalid instruction)
+# But not: sub.w sp, r7, #8
# CHECK-NEXT: pop.w {r4, r5, r7, lr}
# CHECK-NEXT: add sp, #16
# CHECK-NEXT: bx lr
@@ -63,7 +64,7 @@
0x2a 0x46
0x00 0x9b
0xfd 0xf7 0x9d 0xff
-0xa7 0xf1 0x08 0x0d
+# 0xa7 0xf1 0x08 0x0d
0xbd 0xe8 0xb0 0x40
0x04 0xb0
0x70 0x47
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=128913&r1=128912&r2=128913&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Tue Apr 5 14:42:11 2011
@@ -42,8 +42,8 @@
# CHECK: ldrd r0, r1, [r7, #64]!
0xf7 0xe9 0x10 0x01
-# CHECK: lsls.w r0, pc, #1
-0x5f 0xea 0x4f 0x00
+# CHECK: lsls.w r0, r5, #1
+0x5f 0xea 0x45 0x00
# CHECK: mov r11, r7
0xbb 0x46
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