[llvm-commits] [llvm] r128734 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt test/MC/Disassembler/ARM/invalid-LDRT-arm.txt

[Johnny Chen]

Author: johnny
Date: Fri Apr  1 15:21:38 2011
New Revision: 128734

URL: http://llvm.org/viewvc/llvm-project?rev=128734&view=rev
Log:
Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128734&r1=128733&r2=128734&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Apr  1 15:21:38 2011
@@ -1106,6 +1106,14 @@
     MI.addOperand(MCOperand::CreateImm(Offset));
     OpIdx += 1;
   } else {
+    // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of
+    // A8.6.86 LDRT.  So if Inst{4} != 0 while Inst{25} (getIBit(insn)) == 1,
+    // we should reject this insn as invalid.
+    //
+    // Ditto for LDRBT.
+    if ((Opcode == ARM::LDRT || Opcode == ARM::LDRBT) && (slice(insn,4,4) == 1))
+      return false;
+
     // Disassemble the offset reg (Rm), shift type, and immediate shift length.
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRm(insn))));

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128734&r1=128733&r2=128734&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Fri Apr  1 15:21:38 2011
@@ -45,6 +45,9 @@
 # CHECK:	ldr	r0, [r2], #15
 0x0f 0x00 0x92 0xe4
 
+# CHECK:	ldr	r5, [r7, -r10, lsl #2]
+0x0a 0x51 0x17 0xe7
+
 # CHECK:	ldrh	r0, [r2], #0
 0xb0 0x00 0xd2 0xe0
 

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt?rev=128734&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt Fri Apr  1 15:21:38 2011
@@ -0,0 +1,12 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=0 Name=PHI Format=(42)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction.
+0x10 0x51 0x37 0xe6
+
+