[llvm-commits] [llvm] r128662 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
Johnny Chen
johnny.chen at apple.com
Thu Mar 31 12:28:35 PDT 2011
Author: johnny
Date: Thu Mar 31 14:28:35 2011
New Revision: 128662
URL: http://llvm.org/viewvc/llvm-project?rev=128662&view=rev
Log:
Fix single word and unsigned byte data transfer instruction encodings so that
Inst{4} = 0.
rdar://problem/9213022
Added:
llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128662&r1=128661&r2=128662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Mar 31 14:28:35 2011
@@ -991,6 +991,7 @@
[(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
bits<4> Rt;
bits<17> shift;
+ let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
@@ -1020,6 +1021,7 @@
[(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
bits<4> Rt;
bits<17> shift;
+ let shift{4} = 0; // Inst{4} = 0
let Inst{23} = shift{12}; // U (add = ('U' == 1))
let Inst{19-16} = shift{16-13}; // Rn
let Inst{15-12} = Rt;
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt?rev=128662&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt Thu Mar 31 14:28:35 2011
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# LDR (register) has encoding Inst{4} = 0.
+0xba 0xae 0x9f 0x57
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