[llvm-commits] [llvm] r128635 - in /llvm/trunk: lib/Target/ARM/ARMAddressingModes.h lib/Target/ARM/ARMBaseInfo.h lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMInstrFormats.td lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h test/MC/ARM/arm_addrmode2.s
Jim Grosbach
grosbach at apple.com
Thu Mar 31 09:13:34 PDT 2011
Hi Bruno,
I'm glad to see you're looking at this. Hopefully the bugs won't be too hard to track down.
If you're feeling ambitious, addrmode2 is on its way out in favor of addrmode_imm12 and ldst_so_reg. Specifically, addrmode2 conflates the immediate and register addressing and modally indicates which of the two it's defining by the second register operand being zero. This, as I'm sure you've encountered, gives the asm parser all sorts of fun to deal with, as there are operands that aren't part of the assembly syntax and aren't easily inferable without custom handling. Splitting the operand into parts has two major benefits. First, it helps with the above by making the instruction definition only have machine operands which are actually part of the real instructions. Second, the different addressing modes typically have a different scheduling itinerary, and that's not expressive with a combined addressing mode construct. The AI_ldr1 multiclass, used by the base LDR instructions, has an example of how this works.
When you get to doing parsing for the _PRE/_POST instructions that do have associated patterns, there's some complications due to the writeback tied register constraint. The best way we have to represent that right now, albeit kinda ugly, is to use a pseudo-instruction for the code-gen that has the writeback output operand tied to the source base reg, and an assembler-only real instruction (which has the encoding information) that doesn't have an explicit output writeback operand, just the source base operand. The ARMAsmPrinter MC lowering pseudo-expansion would lower the former to the latter.
-Jim
On Mar 31, 2011, at 8:54 AM, Bruno Cardoso Lopes wrote:
> Author: bruno
> Date: Thu Mar 31 10:54:36 2011
> New Revision: 128635
>
> URL: http://llvm.org/viewvc/llvm-project?rev=128635&view=rev
> Log:
> Revert r128632 again, until I figure out what break the tests
>
> Modified:
> llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
> llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
> llvm/trunk/test/MC/ARM/arm_addrmode2.s
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Thu Mar 31 10:54:36 2011
> @@ -408,18 +408,16 @@
> //
> // The first operand is always a Reg. The second operand is a reg if in
> // reg/reg form, otherwise it's reg#0. The third field encodes the operation
> - // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
> - // forth operand 16-17 encodes the index mode.
> + // in bit 12, the immediate in bits 0-11, and the shift op in 13-15.
> //
> // If this addressing mode is a frame index (before prolog/epilog insertion
> // and code rewriting), this operand will have the form: FI#, reg0, <offs>
> // with no shift amount for the frame offset.
> //
> - static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
> - unsigned IdxMode = 0) {
> + static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) {
> assert(Imm12 < (1 << 12) && "Imm too large!");
> bool isSub = Opc == sub;
> - return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
> + return Imm12 | ((int)isSub << 12) | (SO << 13);
> }
> static inline unsigned getAM2Offset(unsigned AM2Opc) {
> return AM2Opc & ((1 << 12)-1);
> @@ -428,10 +426,7 @@
> return ((AM2Opc >> 12) & 1) ? sub : add;
> }
> static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) {
> - return (ShiftOpc)((AM2Opc >> 13) & 7);
> - }
> - static inline unsigned getAM2IdxMode(unsigned AM2Opc) {
> - return (AM2Opc >> 16);
> + return (ShiftOpc)(AM2Opc >> 13);
> }
>
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Thu Mar 31 10:54:36 2011
> @@ -200,59 +200,6 @@
> }
>
> namespace ARMII {
> -
> - /// ARM Index Modes
> - enum IndexMode {
> - IndexModeNone = 0,
> - IndexModePre = 1,
> - IndexModePost = 2,
> - IndexModeUpd = 3
> - };
> -
> - /// ARM Addressing Modes
> - enum AddrMode {
> - AddrModeNone = 0,
> - AddrMode1 = 1,
> - AddrMode2 = 2,
> - AddrMode3 = 3,
> - AddrMode4 = 4,
> - AddrMode5 = 5,
> - AddrMode6 = 6,
> - AddrModeT1_1 = 7,
> - AddrModeT1_2 = 8,
> - AddrModeT1_4 = 9,
> - AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
> - AddrModeT2_i12 = 11,
> - AddrModeT2_i8 = 12,
> - AddrModeT2_so = 13,
> - AddrModeT2_pc = 14, // +/- i12 for pc relative data
> - AddrModeT2_i8s4 = 15, // i8 * 4
> - AddrMode_i12 = 16
> - };
> -
> - inline static const char *AddrModeToString(AddrMode addrmode) {
> - switch (addrmode) {
> - default: llvm_unreachable("Unknown memory operation");
> - case AddrModeNone: return "AddrModeNone";
> - case AddrMode1: return "AddrMode1";
> - case AddrMode2: return "AddrMode2";
> - case AddrMode3: return "AddrMode3";
> - case AddrMode4: return "AddrMode4";
> - case AddrMode5: return "AddrMode5";
> - case AddrMode6: return "AddrMode6";
> - case AddrModeT1_1: return "AddrModeT1_1";
> - case AddrModeT1_2: return "AddrModeT1_2";
> - case AddrModeT1_4: return "AddrModeT1_4";
> - case AddrModeT1_s: return "AddrModeT1_s";
> - case AddrModeT2_i12: return "AddrModeT2_i12";
> - case AddrModeT2_i8: return "AddrModeT2_i8";
> - case AddrModeT2_so: return "AddrModeT2_so";
> - case AddrModeT2_pc: return "AddrModeT2_pc";
> - case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
> - case AddrMode_i12: return "AddrMode_i12";
> - }
> - }
> -
> /// Target Operand Flag enum.
> enum TOF {
> //===------------------------------------------------------------------===//
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Mar 31 10:54:36 2011
> @@ -34,7 +34,25 @@
>
> //===------------------------------------------------------------------===//
> // This four-bit field describes the addressing mode used.
> - AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
> +
> + AddrModeMask = 0x1f,
> + AddrModeNone = 0,
> + AddrMode1 = 1,
> + AddrMode2 = 2,
> + AddrMode3 = 3,
> + AddrMode4 = 4,
> + AddrMode5 = 5,
> + AddrMode6 = 6,
> + AddrModeT1_1 = 7,
> + AddrModeT1_2 = 8,
> + AddrModeT1_4 = 9,
> + AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
> + AddrModeT2_i12 = 11,
> + AddrModeT2_i8 = 12,
> + AddrModeT2_so = 13,
> + AddrModeT2_pc = 14, // +/- i12 for pc relative data
> + AddrModeT2_i8s4 = 15, // i8 * 4
> + AddrMode_i12 = 16,
>
> // Size* - Flags to keep track of the size of an instruction.
> SizeShift = 5,
> @@ -46,9 +64,11 @@
>
> // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
> // and store ops only. Generic "updating" flag is used for ld/st multiple.
> - // The index mode enums are declared in ARMBaseInfo.h
> IndexModeShift = 8,
> IndexModeMask = 3 << IndexModeShift,
> + IndexModePre = 1,
> + IndexModePost = 2,
> + IndexModeUpd = 3,
>
> //===------------------------------------------------------------------===//
> // Instruction encoding formats.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu Mar 31 10:54:36 2011
> @@ -515,15 +515,15 @@
> : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
> pattern> {
> // AM2 store w/ two operands: (GPR, am2offset)
> - // {17-14} Rn
> // {13} 1 == Rm, 0 == imm12
> // {12} isAdd
> // {11-0} imm12/Rm
> - bits<18> addr;
> - let Inst{25} = addr{13};
> - let Inst{23} = addr{12};
> - let Inst{19-16} = addr{17-14};
> - let Inst{11-0} = addr{11-0};
> + bits<14> offset;
> + bits<4> Rn;
> + let Inst{25} = offset{13};
> + let Inst{23} = offset{12};
> + let Inst{19-16} = Rn;
> + let Inst{11-0} = offset{11-0};
> }
>
> // addrmode3 instructions
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Mar 31 10:54:36 2011
> @@ -498,12 +498,6 @@
> let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
> }
>
> -def MemMode2AsmOperand : AsmOperandClass {
> - let Name = "MemMode2";
> - let SuperClasses = [];
> - let ParserMethod = "tryParseMemMode2Operand";
> -}
> -
> // addrmode2 := reg +/- imm12
> // := reg +/- reg shop imm
> //
> @@ -511,7 +505,6 @@
> ComplexPattern<i32, 3, "SelectAddrMode2", []> {
> let EncoderMethod = "getAddrMode2OpValue";
> let PrintMethod = "printAddrMode2Operand";
> - let ParserMatchClass = MemMode2AsmOperand;
> let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
> }
>
> @@ -1663,21 +1656,20 @@
> let Inst{23} = addr{12};
> let Inst{19-16} = addr{17-14};
> let Inst{11-0} = addr{11-0};
> - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
> }
> def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
> - (ins addrmode2:$addr), IndexModePost, LdFrm, itin,
> - opc, "\t$Rt, $addr", "$addr.base = $Rn_wb", []> {
> - // {17-14} Rn
> + (ins GPR:$Rn, am2offset:$offset),
> + IndexModePost, LdFrm, itin,
> + opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
> // {13} 1 == Rm, 0 == imm12
> // {12} isAdd
> // {11-0} imm12/Rm
> - bits<18> addr;
> - let Inst{25} = addr{13};
> - let Inst{23} = addr{12};
> - let Inst{19-16} = addr{17-14};
> - let Inst{11-0} = addr{11-0};
> - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
> + bits<14> offset;
> + bits<4> Rn;
> + let Inst{25} = offset{13};
> + let Inst{23} = offset{12};
> + let Inst{19-16} = Rn;
> + let Inst{11-0} = offset{11-0};
> }
> }
>
> @@ -1722,35 +1714,17 @@
>
> // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
> let mayLoad = 1, neverHasSideEffects = 1 in {
> -def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
> - (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
> - "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
> - // {17-14} Rn
> - // {13} 1 == Rm, 0 == imm12
> - // {12} isAdd
> - // {11-0} imm12/Rm
> - bits<18> addr;
> - let Inst{25} = addr{13};
> - let Inst{23} = addr{12};
> +def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
> + (ins GPR:$base, am2offset:$offset), IndexModePost,
> + LdFrm, IIC_iLoad_ru,
> + "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
> let Inst{21} = 1; // overwrite
> - let Inst{19-16} = addr{17-14};
> - let Inst{11-0} = addr{11-0};
> - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
> -}
> -def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
> - (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
> - "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
> - // {17-14} Rn
> - // {13} 1 == Rm, 0 == imm12
> - // {12} isAdd
> - // {11-0} imm12/Rm
> - bits<18> addr;
> - let Inst{25} = addr{13};
> - let Inst{23} = addr{12};
> +}
> +def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
> + (ins GPR:$base, am2offset:$offset), IndexModePost,
> + LdFrm, IIC_iLoad_bh_ru,
> + "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
> let Inst{21} = 1; // overwrite
> - let Inst{19-16} = addr{17-14};
> - let Inst{11-0} = addr{11-0};
> - let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
> }
> def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
> (ins GPR:$base, am3offset:$offset), IndexModePost,
> @@ -1844,20 +1818,20 @@
>
> // STRT, STRBT, and STRHT are for disassembly only.
>
> -def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
> +def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
> + (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
> IndexModePost, StFrm, IIC_iStore_ru,
> - "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
> + "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
> [/* For disassembly only; pattern left blank */]> {
> let Inst{21} = 1; // overwrite
> - let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
> }
>
> -def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
> +def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
> + (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
> IndexModePost, StFrm, IIC_iStore_bh_ru,
> - "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
> + "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
> [/* For disassembly only; pattern left blank */]> {
> let Inst{21} = 1; // overwrite
> - let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
> }
>
> def STRHT: AI3sthpo<(outs GPR:$base_wb),
> @@ -3417,9 +3391,8 @@
> let Inst{23-20} = opc1;
> }
>
> -class ACI<dag oops, dag iops, string opc, string asm,
> - IndexMode im = IndexModeNone>
> - : I<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
> +class ACI<dag oops, dag iops, string opc, string asm>
> + : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
> opc, asm, "", [/* For disassembly only; pattern left blank */]> {
> let Inst{27-25} = 0b110;
> }
> @@ -3438,7 +3411,7 @@
>
> def _PRE : ACI<(outs),
> (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
> - opc, "\tp$cop, cr$CRd, $addr!", IndexModePre> {
> + opc, "\tp$cop, cr$CRd, $addr!"> {
> let Inst{31-28} = op31_28;
> let Inst{24} = 1; // P = 1
> let Inst{21} = 1; // W = 1
> @@ -3447,8 +3420,8 @@
> }
>
> def _POST : ACI<(outs),
> - (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
> - opc, "\tp$cop, cr$CRd, $addr", IndexModePost> {
> + (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
> + opc, "\tp$cop, cr$CRd, [$base], $offset"> {
> let Inst{31-28} = op31_28;
> let Inst{24} = 0; // P = 0
> let Inst{21} = 1; // W = 1
> @@ -3479,7 +3452,7 @@
>
> def L_PRE : ACI<(outs),
> (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
> - !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
> + !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
> let Inst{31-28} = op31_28;
> let Inst{24} = 1; // P = 1
> let Inst{21} = 1; // W = 1
> @@ -3488,8 +3461,8 @@
> }
>
> def L_POST : ACI<(outs),
> - (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
> - !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr", IndexModePost> {
> + (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
> + !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
> let Inst{31-28} = op31_28;
> let Inst{24} = 0; // P = 0
> let Inst{21} = 1; // W = 1
>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Mar 31 10:54:36 2011
> @@ -48,8 +48,7 @@
> bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
> bool TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
> bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
> - bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
> - ARMII::AddrMode AddrMode);
> + bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
> bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
> bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
> const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
> @@ -96,14 +95,6 @@
> SmallVectorImpl<MCParsedAsmOperand*>&);
> OperandMatchResultTy tryParseMSRMaskOperand(
> SmallVectorImpl<MCParsedAsmOperand*>&);
> - OperandMatchResultTy tryParseMemMode2Operand(
> - SmallVectorImpl<MCParsedAsmOperand*>&);
> -
> - // Asm Match Converter Methods
> - bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
> - const SmallVectorImpl<MCParsedAsmOperand*> &);
> - bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
> - const SmallVectorImpl<MCParsedAsmOperand*> &);
>
> public:
> ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
> @@ -181,7 +172,6 @@
>
> /// Combined record for all forms of ARM address expressions.
> struct {
> - ARMII::AddrMode AddrMode;
> unsigned BaseRegNum;
> union {
> unsigned RegNum; ///< Offset register num, when OffsetIsReg.
> @@ -303,9 +293,7 @@
>
> /// @name Memory Operand Accessors
> /// @{
> - ARMII::AddrMode getMemAddrMode() const {
> - return Mem.AddrMode;
> - }
> +
> unsigned getMemBaseRegNum() const {
> return Mem.BaseRegNum;
> }
> @@ -350,27 +338,6 @@
> bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
> bool isMemory() const { return Kind == Memory; }
> bool isShifter() const { return Kind == Shifter; }
> - bool isMemMode2() const {
> - if (getMemAddrMode() != ARMII::AddrMode2)
> - return false;
> -
> - if (getMemOffsetIsReg())
> - return true;
> -
> - if (getMemNegative() &&
> - !(getMemPostindexed() || getMemPreindexed()))
> - return false;
> -
> - const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
> - if (!CE) return false;
> - int64_t Value = CE->getValue();
> -
> - // The offset must be in the range 0-4095 (imm12).
> - if (Value > 4095 || Value < -4095)
> - return false;
> -
> - return true;
> - }
> bool isMemMode5() const {
> if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
> getMemNegative())
> @@ -498,47 +465,6 @@
> "No offset operand support in mode 7");
> }
>
> - void addMemMode2Operands(MCInst &Inst, unsigned N) const {
> - assert(isMemMode2() && "Invalid mode or number of operands!");
> - Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
> - unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
> -
> - if (getMemOffsetIsReg()) {
> - Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
> -
> - ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
> - ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
> - int64_t ShiftAmount = 0;
> -
> - if (getMemOffsetRegShifted()) {
> - ShOpc = getMemShiftType();
> - const MCConstantExpr *CE =
> - dyn_cast<MCConstantExpr>(getMemShiftAmount());
> - ShiftAmount = CE->getValue();
> - }
> -
> - Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
> - ShOpc, IdxMode)));
> - return;
> - }
> -
> - // Create a operand placeholder to always yield the same number of operands.
> - Inst.addOperand(MCOperand::CreateReg(0));
> -
> - // FIXME: #-0 is encoded differently than #0. Does the parser preserve
> - // the difference?
> - const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
> - assert(CE && "Non-constant mode 2 offset operand!");
> - int64_t Offset = CE->getValue();
> -
> - if (Offset >= 0)
> - Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
> - Offset, ARM_AM::no_shift, IdxMode)));
> - else
> - Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
> - -Offset, ARM_AM::no_shift, IdxMode)));
> - }
> -
> void addMemMode5Operands(MCInst &Inst, unsigned N) const {
> assert(N == 2 && isMemMode5() && "Invalid number of operands!");
>
> @@ -673,9 +599,9 @@
> return Op;
> }
>
> - static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
> - bool OffsetIsReg, const MCExpr *Offset,
> - int OffsetRegNum, bool OffsetRegShifted,
> + static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
> + const MCExpr *Offset, int OffsetRegNum,
> + bool OffsetRegShifted,
> enum ARM_AM::ShiftOpc ShiftType,
> const MCExpr *ShiftAmount, bool Preindexed,
> bool Postindexed, bool Negative, bool Writeback,
> @@ -692,7 +618,6 @@
> "Cannot have expression offset and register offset!");
>
> ARMOperand *Op = new ARMOperand(Memory);
> - Op->Mem.AddrMode = AddrMode;
> Op->Mem.BaseRegNum = BaseRegNum;
> Op->Mem.OffsetIsReg = OffsetIsReg;
> if (OffsetIsReg)
> @@ -764,8 +689,7 @@
> break;
> case Memory:
> OS << "<memory "
> - << "am:" << ARMII::AddrModeToString(getMemAddrMode())
> - << " base:" << getMemBaseRegNum();
> + << "base:" << getMemBaseRegNum();
> if (getMemOffsetIsReg()) {
> OS << " offset:<register " << getMemOffsetRegNum();
> if (getMemOffsetRegShifted()) {
> @@ -1208,57 +1132,13 @@
> return MatchOperand_Success;
> }
>
> -/// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
> -ARMAsmParser::OperandMatchResultTy ARMAsmParser::
> -tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
> - SMLoc S = Parser.getTok().getLoc();
> - const AsmToken &Tok = Parser.getTok();
> - assert(Tok.is(AsmToken::LBrac) && "Token is not a \"[\"");
> -
> - if (ParseMemory(Operands, ARMII::AddrMode2))
> - return MatchOperand_NoMatch;
> -
> - return MatchOperand_Success;
> -}
> -
> -/// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
> -/// Needed here because the Asm Gen Matcher can't handle properly tied operands
> -/// when they refer multiple MIOperands inside a single one.
> -bool ARMAsmParser::
> -CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
> - const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
> - ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
> -
> - // Create a writeback register dummy placeholder.
> - Inst.addOperand(MCOperand::CreateImm(0));
> -
> - ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
> - ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
> - return true;
> -}
> -
> -/// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
> -/// Needed here because the Asm Gen Matcher can't handle properly tied operands
> -/// when they refer multiple MIOperands inside a single one.
> -bool ARMAsmParser::
> -CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
> - const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
> - // Create a writeback register dummy placeholder.
> - Inst.addOperand(MCOperand::CreateImm(0));
> - ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
> - ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
> - ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
> - return true;
> -}
> -
> /// Parse an ARM memory expression, return false if successful else return true
> /// or an error. The first token must be a '[' when called.
> ///
> /// TODO Only preindexing and postindexing addressing are started, unindexed
> /// with option, etc are still to do.
> bool ARMAsmParser::
> -ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
> - ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
> +ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
> SMLoc S, E;
> assert(Parser.getTok().is(AsmToken::LBrac) &&
> "Token is not a Left Bracket");
> @@ -1316,9 +1196,6 @@
> ExclaimTok.getLoc());
> Writeback = true;
> Parser.Lex(); // Eat exclaim token
> - } else { // In addressing mode 2, pre-indexed mode always end with "!"
> - if (AddrMode == ARMII::AddrMode2)
> - Preindexed = false;
> }
> } else {
> // The "[Rn" we have so far was not followed by a comma.
> @@ -1354,10 +1231,11 @@
> Offset = MCConstantExpr::Create(0, getContext());
> }
>
> - Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
> - Offset, OffsetRegNum, OffsetRegShifted,
> - ShiftType, ShiftAmount, Preindexed,
> - Postindexed, Negative, Writeback, S, E));
> + Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
> + OffsetRegNum, OffsetRegShifted,
> + ShiftType, ShiftAmount, Preindexed,
> + Postindexed, Negative, Writeback,
> + S, E));
> if (WBOp)
> Operands.push_back(WBOp);
>
>
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Thu Mar 31 10:54:36 2011
> @@ -643,11 +643,8 @@
> if (PW) {
> MI.addOperand(MCOperand::CreateReg(0));
> ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
> - const TargetInstrDesc &TID = ARMInsts[Opcode];
> - unsigned IndexMode =
> - (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
> unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
> - ARM_AM::no_shift, IndexMode);
> + ARM_AM::no_shift);
> MI.addOperand(MCOperand::CreateImm(Offset));
> OpIdx = 5;
> } else {
> @@ -1076,8 +1073,6 @@
> return false;
>
> ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
> - unsigned IndexMode =
> - (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
> if (getIBit(insn) == 0) {
> // For pre- and post-indexed case, add a reg0 operand (Addressing Mode #2).
> // Otherwise, skip the reg operand since for addrmode_imm12, Rn has already
> @@ -1089,8 +1084,7 @@
>
> // Disassemble the 12-bit immediate offset.
> unsigned Imm12 = slice(insn, 11, 0);
> - unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift,
> - IndexMode);
> + unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
> MI.addOperand(MCOperand::CreateImm(Offset));
> OpIdx += 1;
> } else {
> @@ -1105,7 +1099,7 @@
> // A8.4.1. Possible rrx or shift amount of 32...
> getImmShiftSE(ShOp, ShImm);
> MI.addOperand(MCOperand::CreateImm(
> - ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp, IndexMode)));
> + ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
> OpIdx += 2;
> }
>
>
> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Thu Mar 31 10:54:36 2011
> @@ -181,12 +181,18 @@
> }
> }
>
> -void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
> - raw_ostream &O) {
> +
> +void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
> + raw_ostream &O) {
> const MCOperand &MO1 = MI->getOperand(Op);
> const MCOperand &MO2 = MI->getOperand(Op+1);
> const MCOperand &MO3 = MI->getOperand(Op+2);
>
> + if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
> + printOperand(MI, Op, O);
> + return;
> + }
> +
> O << "[" << getRegisterName(MO1.getReg());
>
> if (!MO2.getReg()) {
> @@ -209,50 +215,6 @@
> O << "]";
> }
>
> -void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
> - raw_ostream &O) {
> - const MCOperand &MO1 = MI->getOperand(Op);
> - const MCOperand &MO2 = MI->getOperand(Op+1);
> - const MCOperand &MO3 = MI->getOperand(Op+2);
> -
> - O << "[" << getRegisterName(MO1.getReg()) << "], ";
> -
> - if (!MO2.getReg()) {
> - unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
> - O << '#'
> - << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
> - << ImmOffs;
> - return;
> - }
> -
> - O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
> - << getRegisterName(MO2.getReg());
> -
> - if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
> - O << ", "
> - << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
> - << " #" << ShImm;
> -}
> -
> -void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
> - raw_ostream &O) {
> - const MCOperand &MO1 = MI->getOperand(Op);
> -
> - if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
> - printOperand(MI, Op, O);
> - return;
> - }
> -
> - const MCOperand &MO3 = MI->getOperand(Op+2);
> - unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
> -
> - if (IdxMode == ARMII::IndexModePost) {
> - printAM2PostIndexOp(MI, Op, O);
> - return;
> - }
> - printAM2PreOrOffsetIndexOp(MI, Op, O);
> -}
> -
> void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
> unsigned OpNum,
> raw_ostream &O) {
>
> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Thu Mar 31 10:54:36 2011
> @@ -42,11 +42,7 @@
> void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
>
> void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
> -
> void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
> - void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
> - void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
> - raw_ostream &O);
> void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
> raw_ostream &O);
> void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
>
> Modified: llvm/trunk/test/MC/ARM/arm_addrmode2.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode2.s?rev=128635&r1=128634&r2=128635&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/arm_addrmode2.s (original)
> +++ llvm/trunk/test/MC/ARM/arm_addrmode2.s Thu Mar 31 10:54:36 2011
> @@ -1,38 +0,0 @@
> -@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
> -
> -@ Post-indexed
> -@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
> -@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
> -@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
> -@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
> -@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
> -@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
> -@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
> -@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
> -@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
> -@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
> -@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
> -@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
> -@ CHECK: ldr r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0x90,0xe6]
> -@ CHECK: ldrb r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xd0,0xe6]
> - ldrt r1, [r0], r2
> - ldrt r1, [r0], r2, lsr #3
> - ldrt r1, [r0], #4
> - ldrbt r1, [r0], r2
> - ldrbt r1, [r0], r2, lsr #3
> - ldrbt r1, [r0], #4
> - strt r1, [r0], r2
> - strt r1, [r0], r2, lsr #3
> - strt r1, [r0], #4
> - strbt r1, [r0], r2
> - strbt r1, [r0], r2, lsr #3
> - strbt r1, [r0], #4
> - ldr r1, [r0], r2, lsr #3
> - ldrb r1, [r0], r2, lsr #3
> -
> -@ Pre-indexed
> -@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
> -@ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
> - ldr r1, [r0, r2, lsr #3]!
> - ldrb r1, [r0, r2, lsr #3]!
> -
>
>
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