[llvm-commits] [llvm] r128299 - in /llvm/trunk: lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h test/MC/Disassembler/ARM/thumb-tests.txt
Johnny Chen
johnny.chen at apple.com
Fri Mar 25 12:35:37 PDT 2011
Author: johnny
Date: Fri Mar 25 14:35:37 2011
New Revision: 128299
URL: http://llvm.org/viewvc/llvm-project?rev=128299&view=rev
Log:
DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.
rdar://problem/9182892
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=128299&r1=128298&r2=128299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Fri Mar 25 14:35:37 2011
@@ -1868,7 +1868,7 @@
OpInfo[1].RegClass == ARM::GPRRegClassID &&
"Expect >= 3 operands and first two as reg operands");
- bool ThreeReg = (OpInfo[2].RegClass == ARM::GPRRegClassID);
+ bool ThreeReg = (OpInfo[2].RegClass > 0);
bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
@@ -1912,7 +1912,8 @@
++OpIdx;
if (ThreeReg) {
- MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+ // This could be an offset register or a TIED_TO register.
+ MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
R2)));
++OpIdx;
}
Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=128299&r1=128298&r2=128299&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Fri Mar 25 14:35:37 2011
@@ -166,3 +166,9 @@
# CHECK: tbb [r5, r4]
0xd5 0xe8 0x04 0xf0
+
+# CHECK: ldr.w r4, [sp, r4, lsl #3]
+0x5d 0xf8 0x34 0x40
+
+# CHECK: ldr.w r5, [r6, #30]
+0x56 0xf8 0x1e 0x56
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