[llvm-commits] [llvm] r128226 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/neon-tests.txt

[Johnny Chen]

Author: johnny
Date: Thu Mar 24 13:40:38 2011
New Revision: 128226

URL: http://llvm.org/viewvc/llvm-project?rev=128226&view=rev
Log:
The r118201 added support for VORR (immediate).  Update ARMDisassemblerCore.cpp to disassemble the
VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128226&r1=128225&r2=128226&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Thu Mar 24 13:40:38 2011
@@ -2302,6 +2302,8 @@
 
 // VMOV (immediate)
 //   Qd/Dd imm
+// VORR (immediate)
+//   Qd/Dd imm src(=Qd/Dd)
 static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode,
     uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
 
@@ -2328,12 +2330,16 @@
   case ARM::VMOVv8i16:
   case ARM::VMVNv4i16:
   case ARM::VMVNv8i16:
+  case ARM::VORRiv4i16:
+  case ARM::VORRiv8i16:
     esize = ESize16;
     break;
   case ARM::VMOVv2i32:
   case ARM::VMOVv4i32:
   case ARM::VMVNv2i32:
   case ARM::VMVNv4i32:
+  case ARM::VORRiv2i32:
+  case ARM::VORRiv4i32:
     esize = ESize32;
     break;
   case ARM::VMOVv1i64:
@@ -2350,6 +2356,16 @@
   MI.addOperand(MCOperand::CreateImm(decodeN1VImm(insn, esize)));
 
   NumOpsAdded = 2;
+
+  // VORRiv*i* variants have an extra $src = $Vd to be filled in.
+  if (NumOps >= 3 &&
+      (OpInfo[2].RegClass == ARM::DPRRegClassID ||
+       OpInfo[2].RegClass == ARM::QPRRegClassID)) {
+    MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[0].RegClass,
+                                                     decodeNEONRd(insn))));
+    NumOpsAdded += 1;
+  }
+
   return true;
 }
 

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt?rev=128226&r1=128225&r2=128226&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt Thu Mar 24 13:40:38 2011
@@ -62,3 +62,6 @@
 
 # CHECK:	vpop	{d8}
 0x02 0x8b 0xbd 0xec
+
+# CHECK:	vorr.i32	q15, #0x4F0000
+0x5f 0xe5 0xc4 0xf2