[llvm-commits] [llvm] r128048 - /llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h

[Matt Beaumont-Gay]

Author: matthewbg
Date: Mon Mar 21 19:37:28 2011
New Revision: 128048

URL: http://llvm.org/viewvc/llvm-project?rev=128048&view=rev
Log:
Avoid -Wunused-variable in -asserts builds

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=128048&r1=128047&r2=128048&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Mon Mar 21 19:37:28 2011
@@ -607,11 +607,6 @@
   const TargetOperandInfo *OpInfo = TID.OpInfo;
   unsigned &OpIdx = NumOpsAdded;
 
-  // Table A6-5 16-bit Thumb Load/store instructions
-  // opA = 0b0101 for STR/LDR (register) and friends.
-  // Otherwise, we have STR/LDR (immediate) and friends.
-  bool Imm5 = (opA != 5);
-
   assert(NumOps >= 2
          && OpInfo[0].RegClass == ARM::tGPRRegClassID
          && OpInfo[1].RegClass == ARM::tGPRRegClassID
@@ -632,7 +627,10 @@
 
   if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
       !OpInfo[OpIdx].isOptionalDef()) {
-    assert(Imm5 && "Immediate operand expected for this opcode");
+    // Table A6-5 16-bit Thumb Load/store instructions
+    // opA = 0b0101 for STR/LDR (register) and friends.
+    // Otherwise, we have STR/LDR (immediate) and friends.
+    assert(opA != 5 && "Immediate operand expected for this opcode");
     MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn)));
     ++OpIdx;
   } else {