[llvm-commits] [llvm] r127935 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt
Johnny Chen
johnny.chen at apple.com
Fri Mar 18 18:16:20 PDT 2011
Author: johnny
Date: Fri Mar 18 20:16:20 2011
New Revision: 127935
URL: http://llvm.org/viewvc/llvm-project?rev=127935&view=rev
Log:
Fixed an assert by the ARM disassembler for LDRD_PRE/POST.
The relevant instruction table entries were changed sometime ago to no longer take
<Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and
add a test case.
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=127935&r1=127934&r2=127935&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Fri Mar 18 20:16:20 2011
@@ -1163,8 +1163,9 @@
decodeRd(insn))));
++OpIdx;
- // Fill in LDRD and STRD's second operand.
- if (DualReg) {
+ // Fill in LDRD and STRD's second operand, but only if it's offset mode OR we
+ // have a pre-or-post-indexed store operation.
+ if (DualReg && (!isPrePost || isStore)) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRd(insn) + 1)));
++OpIdx;
@@ -1186,7 +1187,7 @@
assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected");
assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1))
- && "Index mode or tied_to operand expected");
+ && "Offset mode or tied_to operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
++OpIdx;
Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=127935&r1=127934&r2=127935&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Fri Mar 18 20:16:20 2011
@@ -160,3 +160,6 @@
# CHECK: strdeq r2, r3, [r0], -r8
0xf8 0x24 0x00 0x00
+
+# CHECK: ldrdeq r2, [r0], -r12
+0xdc 0x24 0x00 0x00
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