[llvm-commits] [llvm] r127694 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h test/CodeGen/ARM/vext.ll

[Bob Wilson]

Thanks, Bill.  You're still going to update ARMTargetLowering::isShuffleMaskLegal, right?

On Mar 15, 2011, at 1:47 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Mar 15 15:47:26 2011
> New Revision: 127694
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=127694&view=rev
> Log:
> Some minor cleanups based on feedback.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.h
>    llvm/trunk/test/CodeGen/ARM/vext.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=127694&r1=127693&r2=127694&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Mar 15 15:47:26 2011
> @@ -854,8 +854,6 @@
>   case ARMISD::VTRN:          return "ARMISD::VTRN";
>   case ARMISD::VTBL1:         return "ARMISD::VTBL1";
>   case ARMISD::VTBL2:         return "ARMISD::VTBL2";
> -  case ARMISD::VTBL3:         return "ARMISD::VTBL3";
> -  case ARMISD::VTBL4:         return "ARMISD::VTBL4";
>   case ARMISD::VMULLs:        return "ARMISD::VMULLs";
>   case ARMISD::VMULLu:        return "ARMISD::VMULLu";
>   case ARMISD::BUILD_VECTOR:  return "ARMISD::BUILD_VECTOR";
> @@ -4076,10 +4074,10 @@
>     return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
>                        DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
>                                    &VTBLMask[0], 8));
> -  else
> -    return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 
> -                       DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
> -                                   &VTBLMask[0], 8));
> +
> +  return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 
> +                     DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
> +                                 &VTBLMask[0], 8));
> }
> 
> static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=127694&r1=127693&r2=127694&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Tue Mar 15 15:47:26 2011
> @@ -155,8 +155,6 @@
>       VTRN,         // transpose
>       VTBL1,        // 1-register shuffle with mask
>       VTBL2,        // 2-register shuffle with mask
> -      VTBL3,        // 3-register shuffle with mask
> -      VTBL4,        // 4-register shuffle with mask
> 
>       // Vector multiply long:
>       VMULLs,       // ...signed
> 
> Modified: llvm/trunk/test/CodeGen/ARM/vext.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vext.ll?rev=127694&r1=127693&r2=127694&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/vext.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/vext.ll Tue Mar 15 15:47:26 2011
> @@ -121,3 +121,15 @@
>         %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
>         ret <4 x i16> %tmp2
> }
> +
> +; The actual shuffle code only handles some cases, make sure we check
> +; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
> +; lowering loop can result otherwise).
> +define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
> +;CHECK: test_illegal:
> +;CHECK: vst1.16
> +       %tmp1 = load <8 x i16>* %A
> +       %tmp2 = load <8 x i16>* %B
> +       %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9>
> +       ret <8 x i16> %tmp3
> +}
> 
> 
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