[llvm-commits] [llvm] r127678 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/ps-intrinsics.ll test/CodeGen/XCore/sr-intrinsics.ll

[Richard Osborne]

Author: friedgold
Date: Tue Mar 15 08:45:47 2011
New Revision: 127678

URL: http://llvm.org/viewvc/llvm-project?rev=127678&view=rev
Log:
Add XCore intrinsics for getps, setps, setsr and clrsr.

Added:
    llvm/trunk/test/CodeGen/XCore/ps-intrinsics.ll
    llvm/trunk/test/CodeGen/XCore/sr-intrinsics.ll
Modified:
    llvm/trunk/include/llvm/IntrinsicsXCore.td
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td

Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=127678&r1=127677&r2=127678&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IntrinsicsXCore.td (original)
+++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue Mar 15 08:45:47 2011
@@ -9,8 +9,13 @@
 //===----------------------------------------------------------------------===//
 
 let TargetPrefix = "xcore" in {  // All intrinsics start with "llvm.xcore.".
+  // Miscellaneous instructions.
   def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
   def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
+  def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
+  def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;
+  def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>;
+  def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>;
 
   // Resource instructions.
   def int_xcore_getr : Intrinsic<[llvm_anyptr_ty],[llvm_i32_ty]>;

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=127678&r1=127677&r2=127678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Mar 15 08:45:47 2011
@@ -308,6 +308,16 @@
                  !strconcat(OpcStr, " $b"),
                  [(OpNode immU16:$b)]>;
 }
+multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
+  def _u6: _FU6<
+                 (outs), (ins i32imm:$b),
+                 !strconcat(OpcStr, " $b"),
+                 [(Int immU6:$b)]>;
+  def _lu6: _FLU6<
+                 (outs), (ins i32imm:$b),
+                 !strconcat(OpcStr, " $b"),
+                 [(Int immU16:$b)]>;
+}
 
 multiclass FU6_LU6_np<string OpcStr> {
   def _u6: _FU6<
@@ -638,8 +648,8 @@
 }
 }
 
-// TODO extdp, kentsp, krestsp, blat, setsr
-// clrsr, getsr, kalli
+// TODO extdp, kentsp, krestsp, blat
+// getsr, kalli
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 def BRBU_u6 : _FU6<
                  (outs),
@@ -678,6 +688,10 @@
                     "ldaw r11, cp[$a]",
                     [(set R11, ADDRcpii:$a)]>;
 
+defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
+
+defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
+
 // U10
 // TODO ldwcpl, blacp
 
@@ -818,7 +832,7 @@
 
 // Two operand long
 // TODO setclk, setrdy, setpsc, endin, peek,
-// getd, testlcl, tinitlr, getps, setps
+// getd, testlcl, tinitlr
 def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
                  "bitrev $dst, $src",
                  [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
@@ -839,6 +853,14 @@
                   "settw res[$r], $val",
                   [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
 
+def GETPS_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
+                 "get $dst, ps[$src]",
+                 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
+
+def SETPS_l2r : _FL2R<(outs), (ins GRRegs:$src1, GRRegs:$src2),
+                 "set ps[$src1], $src2",
+                 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
+
 // One operand short
 // TODO edu, eeu, waitet, waitef, tstart, msync, mjoin, clrtp
 // setdp, setcp, setev, kcall

Added: llvm/trunk/test/CodeGen/XCore/ps-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/ps-intrinsics.ll?rev=127678&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/ps-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/XCore/ps-intrinsics.ll Tue Mar 15 08:45:47 2011
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+declare i32 @llvm.xcore.getps(i32)
+declare void @llvm.xcore.setps(i32, i32)
+
+define i32 @getps(i32 %reg) nounwind {
+; CHECK: getps:
+; CHECK: get r0, ps[r0]
+	%result = call i32 @llvm.xcore.getps(i32 %reg)
+	ret i32 %result
+}
+
+
+define void @setps(i32 %reg, i32 %value) nounwind {
+; CHECK: setps:
+; CHECK: set ps[r0], r1
+	call void @llvm.xcore.setps(i32 %reg, i32 %value)
+	ret void
+}

Added: llvm/trunk/test/CodeGen/XCore/sr-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/sr-intrinsics.ll?rev=127678&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/sr-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/XCore/sr-intrinsics.ll Tue Mar 15 08:45:47 2011
@@ -0,0 +1,18 @@
+; RUN: llc < %s -march=xcore | FileCheck %s
+declare void @llvm.xcore.setsr(i32)
+declare void @llvm.xcore.clrsr(i32)
+
+define void @setsr() nounwind {
+; CHECK: setsr:
+; CHECK: setsr 128
+	call void @llvm.xcore.setsr(i32 128)
+	ret void
+}
+
+
+define void @clrsr() nounwind {
+; CHECK: clrsr:
+; CHECK: clrsr 128
+	call void @llvm.xcore.clrsr(i32 128)
+	ret void
+}