[llvm-commits] [llvm] r127646 - in /llvm/trunk/lib/Target/X86: X86InstrFormats.td X86InstrSSE.td
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Mon Mar 14 18:37:55 PDT 2011
Hi Sean,
On Mon, Mar 14, 2011 at 10:28 PM, Sean Callanan <scallanan at apple.com> wrote:
> Author: spyffe
> Date: Mon Mar 14 20:28:15 2011
> New Revision: 127646
>
> URL: http://llvm.org/viewvc/llvm-project?rev=127646&view=rev
> Log:
> Enabled disassembler support for AVX instructions
> in the instruction tables and fixed a few bugs that
> were causing decode conflicts. Rudimentary tests
> are coming up in the next patch.
>
> Modified:
> llvm/trunk/lib/Target/X86/X86InstrFormats.td
> llvm/trunk/lib/Target/X86/X86InstrSSE.td
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=127646&r1=127645&r2=127646&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Mar 14 20:28:15 2011
> @@ -319,7 +319,7 @@
> Requires<[HasAVX]>;
> class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
> list<dag> pattern>
> - : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>,
> + : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedSingle>, TB,
> Requires<[HasAVX]>;
>
> // SSE2 Instruction Templates:
> @@ -353,7 +353,7 @@
> Requires<[HasAVX]>;
> class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
> list<dag> pattern>
> - : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>,
> + : I<o, F, outs, ins, !strconcat("v", asm), pattern, SSEPackedDouble>, TB,
> OpSize, Requires<[HasAVX]>;
>
> // SSE3 Instruction Templates:
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=127646&r1=127645&r2=127646&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Mar 14 20:28:15 2011
> @@ -135,7 +135,7 @@
> // is used instead. Register-to-register movss/movsd is not modeled as an
> // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
> // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
Why not remove isAsmParserOnly completely instead of making it zero?
> def VMOVSSrr : sse12_move_rr<FR32, v4f32,
> "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
> def VMOVSDrr : sse12_move_rr<FR64, v2f64,
> @@ -218,7 +218,7 @@
> "movsd\t{$src, $dst|$dst, $src}",
> [(store FR64:$src, addr:$dst)]>;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
> "movss\t{$src, $dst|$dst, $src}",
> [(store FR32:$src, addr:$dst)]>, XS, VEX;
> @@ -251,7 +251,7 @@
> [(set RC:$dst, (ld_frag addr:$src))], d>;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
> "movaps", SSEPackedSingle>, VEX;
> defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
> @@ -279,7 +279,7 @@
> defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
> "movupd", SSEPackedDouble, 0>, TB, OpSize;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
> "movaps\t{$src, $dst|$dst, $src}",
> [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
> @@ -328,7 +328,7 @@
> [(store (v2f64 VR128:$src), addr:$dst)]>;
>
> // Intrinsic forms of MOVUPS/D load and store
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> let canFoldAsLoad = 1, isReMaterializable = 1 in
> def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
> (ins f128mem:$src),
> @@ -382,7 +382,7 @@
> SSEPackedDouble>, TB, OpSize;
> }
>
> -let isAsmParserOnly = 1, AddedComplexity = 20 in {
> +let isAsmParserOnly = 0, AddedComplexity = 20 in {
> defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
> defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
> @@ -395,7 +395,7 @@
> "\t{$src2, $dst|$dst, $src2}">;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
> "movlps\t{$src, $dst|$dst, $src}",
> [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
> @@ -416,7 +416,7 @@
>
> // v2f64 extract element 1 is always custom lowered to unpack high to low
> // and extract element 0 so the non-store version isn't too horrible.
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
> "movhps\t{$src, $dst|$dst, $src}",
> [(store (f64 (vector_extract
> @@ -441,7 +441,7 @@
> (v2f64 (unpckh VR128:$src, (undef))),
> (iPTR 0))), addr:$dst)]>;
>
> -let isAsmParserOnly = 1, AddedComplexity = 20 in {
> +let isAsmParserOnly = 0, AddedComplexity = 20 in {
> def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src1, VR128:$src2),
> "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -516,7 +516,7 @@
> !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
> "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
> defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
> @@ -591,7 +591,7 @@
> [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
> f32mem, load, "cvtss2si">, XS, VEX;
> defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
> @@ -622,7 +622,7 @@
> f128mem, load, "cvtsd2si{q}">, XD, REX_W;
>
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
> int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
> defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
> @@ -653,7 +653,7 @@
> /// SSE 1 Only
>
> // Aliases for intrinsics
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
> f32mem, load, "cvttss2si">, XS, VEX;
> defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
> @@ -676,7 +676,7 @@
> int_x86_sse2_cvttsd2si64, f128mem, load,
> "cvttsd2si{q}">, XD, REX_W;
>
> -let isAsmParserOnly = 1, Pattern = []<dag> in {
> +let isAsmParserOnly = 0, Pattern = []<dag> in {
> defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
> "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
> defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
> @@ -702,7 +702,7 @@
> /// SSE 2 Only
>
> // Convert scalar double to scalar single
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
> (ins FR64:$src1, FR64:$src2),
> "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
> @@ -723,7 +723,7 @@
> [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
> Requires<[HasSSE2, OptForSize]>;
>
> -let isAsmParserOnly = 1 in
> +let isAsmParserOnly = 0 in
> defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
> int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
> XS, VEX_4V;
> @@ -732,7 +732,7 @@
> int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
>
> // Convert scalar single to scalar double
> -let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
> +let isAsmParserOnly = 0 in { // SSE2 instructions with XS prefix
> def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
> (ins FR32:$src1, FR32:$src2),
> "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -754,7 +754,7 @@
> [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
> Requires<[HasSSE2, OptForSize]>;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
> (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
> "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -788,7 +788,7 @@
> Requires<[HasSSE2, OptForSpeed]>;
>
> // Convert doubleword to packed single/double fp
> -let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
> +let isAsmParserOnly = 0 in { // SSE2 instructions without OpSize prefix
> def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vcvtdq2ps\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
> @@ -810,7 +810,7 @@
> TB, Requires<[HasSSE2]>;
>
> // FIXME: why the non-intrinsic version is described as SSE3?
> -let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
> +let isAsmParserOnly = 0 in { // SSE2 instructions with XS prefix
> def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vcvtdq2pd\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
> @@ -833,7 +833,7 @@
>
>
> // Convert packed single/double fp to doubleword
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
> def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
> @@ -848,7 +848,7 @@
> def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
> "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "cvtps2dq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
> @@ -867,7 +867,7 @@
> [(set VR128:$dst, (int_x86_sse2_cvtps2dq
> (memop addr:$src)))]>;
>
> -let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
> +let isAsmParserOnly = 0 in { // SSE2 packed instructions with XD prefix
> def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vcvtpd2dq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
> @@ -890,7 +890,7 @@
>
>
> // Convert with truncation packed single/double fp to doubleword
> -let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
> +let isAsmParserOnly = 0 in { // SSE2 packed instructions with XS prefix
> def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
> def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
> @@ -910,7 +910,7 @@
> (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
>
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vcvttps2dq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst,
> @@ -923,7 +923,7 @@
> XS, VEX, Requires<[HasAVX]>;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src),
> "cvttpd2dq\t{$src, $dst|$dst, $src}",
> @@ -943,7 +943,7 @@
> [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
> (memop addr:$src)))]>;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> // The assembler can recognize rr 256-bit instructions by seeing a ymm
> // register, but the same isn't true when using memory operands instead.
> // Provide other assembly rr and rm forms to address this explicitly.
> @@ -966,7 +966,7 @@
> }
>
> // Convert packed single to packed double
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> // SSE2 instructions without OpSize prefix
> def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
> @@ -982,7 +982,7 @@
> def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
> "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vcvtps2pd\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
> @@ -1004,7 +1004,7 @@
> TB, Requires<[HasSSE2]>;
>
> // Convert packed double to packed single
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> // The assembler can recognize rr 256-bit instructions by seeing a ymm
> // register, but the same isn't true when using memory operands instead.
> // Provide other assembly rr and rm forms to address this explicitly.
> @@ -1031,7 +1031,7 @@
> "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
>
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "cvtpd2ps\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
> @@ -1089,26 +1089,27 @@
> // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
> multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
> string asm, string asm_alt> {
> - def rr : SIi8<0xC2, MRMSrcReg,
> - (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
> - asm, []>;
> - let mayLoad = 1 in
> - def rm : SIi8<0xC2, MRMSrcMem,
> - (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
> - asm, []>;
> - // Accept explicit immediate argument form instead of comparison code.
> let isAsmParserOnly = 1 in {
> - def rr_alt : SIi8<0xC2, MRMSrcReg,
> - (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
> - asm_alt, []>;
> + def rr : SIi8<0xC2, MRMSrcReg,
> + (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
> + asm, []>;
> let mayLoad = 1 in
> - def rm_alt : SIi8<0xC2, MRMSrcMem,
> - (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
> - asm_alt, []>;
> + def rm : SIi8<0xC2, MRMSrcMem,
> + (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
> + asm, []>;
> }
> +
> + // Accept explicit immediate argument form instead of comparison code.
> + def rr_alt : SIi8<0xC2, MRMSrcReg,
> + (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
> + asm_alt, []>;
> + let mayLoad = 1 in
> + def rm_alt : SIi8<0xC2, MRMSrcMem,
> + (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
> + asm_alt, []>;
> }
>
> -let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
> +let neverHasSideEffects = 1, isAsmParserOnly = 0 in {
> defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
> "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
> "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
> @@ -1141,7 +1142,7 @@
> }
>
> // Aliases to match intrinsics which expect XMM operand(s).
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
> "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
> XS, VEX_4V;
> @@ -1171,7 +1172,7 @@
> }
>
> let Defs = [EFLAGS] in {
> - let isAsmParserOnly = 1 in {
> + let isAsmParserOnly = 0 in {
> defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
> "ucomiss", SSEPackedSingle>, VEX;
> defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
> @@ -1220,24 +1221,25 @@
> multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
> Intrinsic Int, string asm, string asm_alt,
> Domain d> {
> - def rri : PIi8<0xC2, MRMSrcReg,
> - (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
> - [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
> - def rmi : PIi8<0xC2, MRMSrcMem,
> - (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
> - [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
> - // Accept explicit immediate argument form instead of comparison code.
> let isAsmParserOnly = 1 in {
> - def rri_alt : PIi8<0xC2, MRMSrcReg,
> - (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
> - asm_alt, [], d>;
> - def rmi_alt : PIi8<0xC2, MRMSrcMem,
> - (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
> - asm_alt, [], d>;
> + def rri : PIi8<0xC2, MRMSrcReg,
> + (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
> + [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
> + def rmi : PIi8<0xC2, MRMSrcMem,
> + (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
> + [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
> }
> +
> + // Accept explicit immediate argument form instead of comparison code.
> + def rri_alt : PIi8<0xC2, MRMSrcReg,
> + (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
> + asm_alt, [], d>;
> + def rmi_alt : PIi8<0xC2, MRMSrcMem,
> + (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
> + asm_alt, [], d>;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
> "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
> "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
> @@ -1294,19 +1296,19 @@
> (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
> }
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
> "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
> - memopv4f32, SSEPackedSingle>, VEX_4V;
> + memopv4f32, SSEPackedSingle>, TB, VEX_4V;
> defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
> "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
> - memopv8f32, SSEPackedSingle>, VEX_4V;
> + memopv8f32, SSEPackedSingle>, TB, VEX_4V;
> defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
> "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
> - memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
> + memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
> defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
> "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
> - memopv4f64, SSEPackedDouble>, OpSize, VEX_4V;
> + memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
> }
>
> let Constraints = "$src1 = $dst" in {
> @@ -1340,7 +1342,7 @@
> }
>
> let AddedComplexity = 10 in {
> - let isAsmParserOnly = 1 in {
> + let isAsmParserOnly = 0 in {
> defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
> VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> SSEPackedSingle>, VEX_4V;
> @@ -1404,7 +1406,7 @@
> defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
> SSEPackedDouble>, TB, OpSize;
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
> "movmskps", SSEPackedSingle>, VEX;
> defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
> @@ -1482,7 +1484,7 @@
> ///
> multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
> SDNode OpNode> {
> - let isAsmParserOnly = 1 in {
> + let isAsmParserOnly = 0 in {
> defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
> FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
>
> @@ -1514,7 +1516,7 @@
> multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
> SDNode OpNode, int HasPat = 0,
> list<list<dag>> Pattern = []> {
> - let isAsmParserOnly = 1, Pattern = []<dag> in {
> + let isAsmParserOnly = 0, Pattern = []<dag> in {
> defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
> !strconcat(OpcodeStr, "ps"), f128mem,
> !if(HasPat, Pattern[0], // rr
> @@ -1561,7 +1563,7 @@
>
> /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
> ///
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
> defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
> !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
> @@ -1667,7 +1669,7 @@
> }
>
> // Binary Arithmetic instructions
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
> basic_sse12_fp_binop_s_int<0x58, "add", 0>,
> basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
> @@ -1899,7 +1901,7 @@
> [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> // Square root.
> defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
> sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
> @@ -1955,7 +1957,7 @@
> // SSE 1 & 2 - Non-temporal stores
> //===----------------------------------------------------------------------===//
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
> (ins i128mem:$dst, VR128:$src),
> "movntps\t{$src, $dst|$dst, $src}",
> @@ -2138,7 +2140,7 @@
> // SSE 1 & 2 - Load/Store XCSR register
> //===----------------------------------------------------------------------===//
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
> "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
> def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
> @@ -2156,7 +2158,7 @@
>
> let ExeDomain = SSEPackedInt in { // SSE integer instructions
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> let neverHasSideEffects = 1 in {
> def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
> @@ -2226,7 +2228,7 @@
> }
>
> // Intrinsic forms of MOVDQU load and store
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> let canFoldAsLoad = 1 in
> def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
> "vmovdqu\t{$src, $dst|$dst, $src}",
> @@ -2347,7 +2349,7 @@
>
> // 128-bit Integer Arithmetic
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
> defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
> defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
> @@ -2437,7 +2439,7 @@
> // SSE2 - Packed Integer Logical Instructions
> //===---------------------------------------------------------------------===//
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
> int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
> VEX_4V;
> @@ -2584,7 +2586,7 @@
> // SSE2 - Packed Integer Comparison Instructions
> //===---------------------------------------------------------------------===//
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
> 0>, VEX_4V;
> defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
> @@ -2638,7 +2640,7 @@
> // SSE2 - Packed Integer Pack Instructions
> //===---------------------------------------------------------------------===//
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
> 0, 0>, VEX_4V;
> defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
> @@ -2676,7 +2678,7 @@
> }
> } // ExeDomain = SSEPackedInt
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> let AddedComplexity = 5 in
> defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
> VEX;
> @@ -2724,7 +2726,7 @@
> addr:$src2))))]>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
> 0>, VEX_4V;
> defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
> @@ -2834,7 +2836,7 @@
> }
>
> // Extract
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
> (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
> "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -2847,7 +2849,7 @@
> imm:$src2))]>;
>
> // Insert
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
> def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
> @@ -2866,7 +2868,7 @@
>
> let ExeDomain = SSEPackedInt in {
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
> "pmovmskb\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
> @@ -2885,7 +2887,7 @@
>
> let ExeDomain = SSEPackedInt in {
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> let Uses = [EDI] in
> def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
> (ins VR128:$src, VR128:$mask),
> @@ -2914,7 +2916,7 @@
> //===---------------------------------------------------------------------===//
>
> // Move Int Doubleword to Packed Double Int
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
> "movd\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst,
> @@ -2943,7 +2945,7 @@
>
>
> // Move Int Doubleword to Single Scalar
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
> "movd\t{$src, $dst|$dst, $src}",
> [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
> @@ -2962,7 +2964,7 @@
> [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
>
> // Move Packed Doubleword Int to Packed Double Int
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
> "movd\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
> @@ -2998,7 +3000,7 @@
> [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
>
> // Move Scalar Single to Double Int
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
> "movd\t{$src, $dst|$dst, $src}",
> [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
> @@ -3014,7 +3016,7 @@
> [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
>
> // movd / movq to XMM register zero-extends
> -let AddedComplexity = 15, isAsmParserOnly = 1 in {
> +let AddedComplexity = 15, isAsmParserOnly = 0 in {
> def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
> "movd\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (v4i32 (X86vzmovl
> @@ -3038,7 +3040,7 @@
> }
>
> let AddedComplexity = 20 in {
> -let isAsmParserOnly = 1 in
> +let isAsmParserOnly = 0 in
> def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
> "movd\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst,
> @@ -3064,7 +3066,7 @@
> //===---------------------------------------------------------------------===//
>
> // Move Quadword Int to Packed Quadword Int
> -let isAsmParserOnly = 1 in
> +let isAsmParserOnly = 0 in
> def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
> "vmovq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst,
> @@ -3077,7 +3079,7 @@
> Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
>
> // Move Packed Quadword Int to Quadword Int
> -let isAsmParserOnly = 1 in
> +let isAsmParserOnly = 0 in
> def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
> "movq\t{$src, $dst|$dst, $src}",
> [(store (i64 (vector_extract (v2i64 VR128:$src),
> @@ -3091,7 +3093,7 @@
> (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
>
> // Store / copy lower 64-bits of a XMM register.
> -let isAsmParserOnly = 1 in
> +let isAsmParserOnly = 0 in
> def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
> "movq\t{$src, $dst|$dst, $src}",
> [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
> @@ -3099,7 +3101,7 @@
> "movq\t{$src, $dst|$dst, $src}",
> [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
>
> -let AddedComplexity = 20, isAsmParserOnly = 1 in
> +let AddedComplexity = 20, isAsmParserOnly = 0 in
> def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
> "vmovq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst,
> @@ -3124,7 +3126,7 @@
>
> // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
> // IA32 document. movq xmm1, xmm2 does clear the high bits.
> -let isAsmParserOnly = 1, AddedComplexity = 15 in
> +let isAsmParserOnly = 0, AddedComplexity = 15 in
> def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vmovq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
> @@ -3135,7 +3137,7 @@
> [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
> XS, Requires<[HasSSE2]>;
>
> -let AddedComplexity = 20, isAsmParserOnly = 1 in
> +let AddedComplexity = 20, isAsmParserOnly = 0 in
> def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
> "vmovq\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (v2i64 (X86vzmovl
> @@ -3153,7 +3155,7 @@
> }
>
> // Instructions to match in the assembler
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
> "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
> def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
> @@ -3167,7 +3169,7 @@
> // xr = XMM register
> // xm = mem64
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
> def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> @@ -3209,7 +3211,7 @@
> //===---------------------------------------------------------------------===//
>
> // Convert Packed Double FP to Packed DW Integers
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> // The assembler can recognize rr 256-bit instructions by seeing a ymm
> // register, but the same isn't true when using memory operands instead.
> // Provide other assembly rr and rm forms to address this explicitly.
> @@ -3237,7 +3239,7 @@
> "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
>
> // Convert Packed DW Integers to Packed Double FP
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
> "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
> def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
> @@ -3288,7 +3290,7 @@
> !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> // FIXME: Merge above classes when we have patterns for the ymm version
> defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
> defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
> @@ -3319,7 +3321,7 @@
> []>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> // FIXME: Merge above classes when we have patterns for the ymm version
> defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
> defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
> @@ -3327,7 +3329,7 @@
> defm MOVDDUP : sse3_replicate_dfp<"movddup">;
>
> // Move Unaligned Integer
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
> "vlddqu\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
> @@ -3391,21 +3393,21 @@
> [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX],
> +let isAsmParserOnly = 0, Predicates = [HasAVX],
> ExeDomain = SSEPackedDouble in {
> defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
> - f128mem, 0>, XD, VEX_4V;
> + f128mem, 0>, TB, XD, VEX_4V;
> defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
> - f128mem, 0>, OpSize, VEX_4V;
> + f128mem, 0>, TB, OpSize, VEX_4V;
> defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
> - f256mem, 0>, XD, VEX_4V;
> + f256mem, 0>, TB, XD, VEX_4V;
> defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
> - f256mem, 0>, OpSize, VEX_4V;
> + f256mem, 0>, TB, OpSize, VEX_4V;
> }
> let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
> ExeDomain = SSEPackedDouble in {
> defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
> - f128mem>, XD;
> + f128mem>, TB, XD;
> defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
> f128mem>, TB, OpSize;
> }
> @@ -3444,7 +3446,7 @@
> [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
> int_x86_sse3_hadd_ps, 0>, VEX_4V;
> defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
> @@ -3496,7 +3498,7 @@
> (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
> int_x86_ssse3_pabs_b_128>, VEX;
> defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
> @@ -3538,7 +3540,7 @@
> (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> let isCommutable = 0 in {
> defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
> int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
> @@ -3630,7 +3632,7 @@
> []>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
> let Constraints = "$src1 = $dst" in
> defm PALIGN : ssse3_palign<"palignr">;
> @@ -3985,7 +3987,7 @@
> OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
> VEX;
> defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
> @@ -4051,7 +4053,7 @@
> OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
> VEX;
> defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
> @@ -4092,7 +4094,7 @@
> OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
> VEX;
> defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
> @@ -4134,7 +4136,7 @@
> // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
> def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
> (ins VR128:$src1, i32i8imm:$src2),
> @@ -4156,7 +4158,7 @@
> // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
>
> defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
> @@ -4178,7 +4180,7 @@
> addr:$dst)]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
>
> defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
> @@ -4199,7 +4201,7 @@
> addr:$dst)]>, OpSize, REX_W;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
>
> defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
> @@ -4222,7 +4224,7 @@
> addr:$dst)]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
> def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
> (ins VR128:$src1, i32i8imm:$src2),
> @@ -4262,7 +4264,7 @@
> imm:$src3))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
> let Constraints = "$src1 = $dst" in
> defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
> @@ -4288,7 +4290,7 @@
> imm:$src3)))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
> let Constraints = "$src1 = $dst" in
> defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
> @@ -4314,7 +4316,7 @@
> imm:$src3)))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
> let Constraints = "$src1 = $dst" in
> defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
> @@ -4347,7 +4349,7 @@
>
> let Constraints = "$src1 = $dst" in
> defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
>
> def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
> @@ -4517,7 +4519,7 @@
> }
>
> // FP round - roundss, roundps, roundsd, roundpd
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> // Intrinsic form
> defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
> memopv4f32, memopv2f64,
> @@ -4552,7 +4554,7 @@
>
> // ptest instruction we'll lower to this in X86ISelLowering primarily from
> // the intel intrinsic that corresponds to this.
> -let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let Defs = [EFLAGS], isAsmParserOnly = 0, Predicates = [HasAVX] in {
> def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
> "vptest\t{$src2, $src1|$src1, $src2}",
> [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
> @@ -4595,7 +4597,7 @@
> OpSize, VEX;
> }
>
> -let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let Defs = [EFLAGS], isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
> defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
> defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
> @@ -4644,7 +4646,7 @@
> (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
> int_x86_sse41_phminposuw>, VEX;
> defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
> @@ -4670,7 +4672,7 @@
> (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> let isCommutable = 0 in
> defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
> 0>, VEX_4V;
> @@ -4737,7 +4739,7 @@
> OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
> let Constraints = "$src1 = $dst" in
> defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
> @@ -4769,7 +4771,7 @@
> OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> let isCommutable = 0 in {
> defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
> VR128, memopv16i8, i128mem, 0>, VEX_4V;
> @@ -4810,7 +4812,7 @@
> }
>
> /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
> RegisterClass RC, X86MemOperand x86memop,
> PatFrag mem_frag, Intrinsic IntId> {
> @@ -4870,7 +4872,7 @@
> def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
> (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
> "vmovntdqa\t{$src, $dst|$dst, $src}",
> [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
> @@ -4904,7 +4906,7 @@
> (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in
> defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
> 0>, VEX_4V;
> let Constraints = "$src1 = $dst" in
> @@ -4936,7 +4938,7 @@
> defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
> }
>
> -let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
> +let Defs = [XMM0, EFLAGS], isAsmParserOnly = 0,
> Predicates = [HasAVX] in {
> def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
> (ins VR128:$src1, VR128:$src2, i8imm:$src3),
> @@ -4972,7 +4974,7 @@
> defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX],
> +let isAsmParserOnly = 0, Predicates = [HasAVX],
> Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
> def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
> (ins VR128:$src1, VR128:$src3, i8imm:$src5),
> @@ -5007,7 +5009,7 @@
> }
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
> VEX;
> defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
> @@ -5046,7 +5048,7 @@
> }
> }
>
> -let isAsmParserOnly = 1, Predicates = [HasAVX] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX] in {
> defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
> VEX;
> defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
> @@ -5165,7 +5167,7 @@
> }
>
> // Perform One Round of an AES Encryption/Decryption Flow
> -let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX, HasAES] in {
> defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
> int_x86_aesni_aesenc, 0>, VEX_4V;
> defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
> @@ -5205,7 +5207,7 @@
> (AESDECLASTrm VR128:$src1, addr:$src2)>;
>
> // Perform the AES InvMixColumn Transformation
> -let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX, HasAES] in {
> def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src1),
> "vaesimc\t{$src1, $dst|$dst, $src1}",
> @@ -5233,7 +5235,7 @@
> OpSize;
>
> // AES Round Key Generation Assist
> -let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
> +let isAsmParserOnly = 0, Predicates = [HasAVX, HasAES] in {
> def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src1, i8imm:$src2),
> "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
> @@ -5269,7 +5271,7 @@
> // Only the AVX version of CLMUL instructions are described here.
>
> // Carry-less Multiplication instructions
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
> def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
> (ins VR128:$src1, VR128:$src2, i8imm:$src3),
> "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
> @@ -5301,7 +5303,7 @@
> // AVX Instructions
> //===----------------------------------------------------------------------===//
>
> -let isAsmParserOnly = 1 in {
> +let isAsmParserOnly = 0 in {
>
> // Load from memory and broadcast to all elements of the destination operand
> class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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