[llvm-commits] [llvm] r127642 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt

[Johnny Chen]

Author: johnny
Date: Mon Mar 14 20:13:17 2011
New Revision: 127642

URL: http://llvm.org/viewvc/llvm-project?rev=127642&view=rev
Log:
Fixed an ARM disassembler bug where it does not handle STRi12 correctly because an extra
register operand was erroneously added.  Remove an incorrect assert which triggers the bug.

rdar://problem/9131529

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=127642&r1=127641&r2=127642&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Mar 14 20:13:17 2011
@@ -1079,18 +1079,21 @@
   if (OpIdx + 1 >= NumOps)
     return false;
 
-  assert((OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) &&
-         (OpInfo[OpIdx+1].RegClass < 0) &&
-         "Expect 1 reg operand followed by 1 imm operand");
-
   ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
   if (getIBit(insn) == 0) {
-    MI.addOperand(MCOperand::CreateReg(0));
+    // For pre- and post-indexed case, add a reg0 operand (Addressing Mode #2).
+    // Otherwise, skip the reg operand since for addrmode_imm12, Rn has already
+    // been populated.
+    if (isPrePost) {
+      MI.addOperand(MCOperand::CreateReg(0));
+      OpIdx += 1;
+    }
 
     // Disassemble the 12-bit immediate offset.
     unsigned Imm12 = slice(insn, 11, 0);
     unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift);
     MI.addOperand(MCOperand::CreateImm(Offset));
+    OpIdx += 1;
   } else {
     // Disassemble the offset reg (Rm), shift type, and immediate shift length.
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
@@ -1104,8 +1107,8 @@
     getImmShiftSE(ShOp, ShImm);
     MI.addOperand(MCOperand::CreateImm(
                     ARM_AM::getAM2Opc(AddrOpcode, ShImm, ShOp)));
+    OpIdx += 2;
   }
-  OpIdx += 2;
 
   return true;
 }

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=127642&r1=127641&r2=127642&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Mon Mar 14 20:13:17 2011
@@ -142,3 +142,15 @@
 
 # CHECK:	uqadd16mi	r6, r11, r8
 0x18 0x60 0x6b 0x46
+
+# CHECK:	str	r0, [sp, #4]
+0x04 0x00 0x8d 0xe5
+
+# CHECK:	str	r1, [sp]
+0x00 0x10 0x8d 0xe5
+
+# CHECK:	ldr	r3, [pc, #144]
+0x90 0x30 0x9f 0xe5
+
+# CHECK:	strdeq	r2, r3, [r0], -r8
+0xf8 0x24 0x00 0x00