[llvm-commits] [llvm] r127508 - /llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Fri Mar 11 17:11:41 2011
New Revision: 127508

URL: http://llvm.org/viewvc/llvm-project?rev=127508&view=rev
Log:
Remove dead code. These ARM instruction definitions no longer exist.

Modified:
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=127508&r1=127507&r2=127508&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Fri Mar 11 17:11:41 2011
@@ -1600,15 +1600,6 @@
         Name == "FNEGDcc")
       return false;
 
-    // Ditto for VNEGDcc and VNEGScc.
-    if (Name == "VNEGDcc" || Name == "VNEGScc")
-      return false;
-
-    // LDMIA_RET is a special case of LDM (Load Multiple) where the registers
-    // loaded include the PC, causing a branch to a loaded address.  Ignore
-    // the LDMIA_RET instruction when decoding.
-    if (Name == "LDMIA_RET") return false;
-
     // Bcc is in a more generic form than B.  Ignore B when decoding.
     if (Name == "B") return false;