[llvm-commits] [llvm] r126995 - in /llvm/trunk: lib/Target/CellSPU/SPUISelDAGToDAG.cpp test/CodeGen/CellSPU/loads.ll test/CodeGen/CellSPU/stores.ll

[Kalle Raiskila]

Author: kraiskil
Date: Fri Mar  4 06:00:11 2011
New Revision: 126995

URL: http://llvm.org/viewvc/llvm-project?rev=126995&view=rev
Log:
Allow load from constant on SPU.
A 'load <4 x i32>* null' crashes llc before this fix.

Modified:
    llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/CellSPU/loads.ll
    llvm/trunk/test/CodeGen/CellSPU/stores.ll

Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=126995&r1=126994&r2=126995&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Fri Mar  4 06:00:11 2011
@@ -321,12 +321,17 @@
   // These match the addr256k operand type:
   EVT OffsVT = MVT::i16;
   SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
+  int64_t val;
 
   switch (N.getOpcode()) {
   case ISD::Constant:
+    val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue();
+    Base = CurDAG->getTargetConstant( val , MVT::i32);
+    Index = Zero;
+    return true; break;
   case ISD::ConstantPool:
   case ISD::GlobalAddress:
-    report_fatal_error("SPU SelectAFormAddr: Constant/Pool/Global not lowered.");
+    report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
     /*NOTREACHED*/
 
   case ISD::TargetConstant:

Modified: llvm/trunk/test/CodeGen/CellSPU/loads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/loads.ll?rev=126995&r1=126994&r2=126995&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/loads.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/loads.ll Fri Mar  4 06:00:11 2011
@@ -50,3 +50,10 @@
   %rv = load i32* %ptr, align 2
   ret i32 %rv
 }
+
+define <4 x i32> @load_null_vec( ) {
+;CHECK: lqa
+;CHECK: bi $lr
+	%rv = load <4 x i32>* null
+	ret <4 x i32> %rv
+}

Modified: llvm/trunk/test/CodeGen/CellSPU/stores.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/stores.ll?rev=126995&r1=126994&r2=126995&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/stores.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/stores.ll Fri Mar  4 06:00:11 2011
@@ -171,3 +171,11 @@
 	store <8 x float> %val, <8 x float>* %ptr
 	ret void
 }
+
+define void @store_null_vec( <4 x i32> %val ) {
+; FIXME - this is for some reason compiled into a il+stqd, not a sta. 
+;CHECK: stqd
+;CHECK: bi $lr
+	store <4 x i32> %val, <4 x i32>* null
+	ret void
+}