[llvm-commits] [llvm] r126915 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp test/MC/Disassembler/ARM/arm-tests.txt utils/TableGen/ARMDecoderEmitter.cpp

[Bob Wilson]

Author: bwilson
Date: Wed Mar  2 19:41:01 2011
New Revision: 126915

URL: http://llvm.org/viewvc/llvm-project?rev=126915&view=rev
Log:
pr9367: Add missing predicated BLX instructions.
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=126915&r1=126914&r2=126915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Mar  2 19:41:01 2011
@@ -1340,7 +1340,16 @@
             Requires<[IsARM, HasV5T, IsNotDarwin]> {
     bits<4> func;
     let Inst{31-4} = 0b1110000100101111111111110011;
-    let Inst{3-0}   = func;
+    let Inst{3-0}  = func;
+  }
+
+  def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
+                    IIC_Br, "blx", "\t$func",
+                    [(ARMcall_pred GPR:$func)]>,
+                 Requires<[IsARM, HasV5T, IsNotDarwin]> {
+    bits<4> func;
+    let Inst{27-4} = 0b000100101111111111110011;
+    let Inst{3-0}  = func;
   }
 
   // ARMv4T
@@ -1389,6 +1398,15 @@
     let Inst{3-0}   = func;
   }
 
+  def BLXr9_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
+                      IIC_Br, "blx", "\t$func",
+                      [(ARMcall_pred GPR:$func)]>,
+                   Requires<[IsARM, HasV5T, IsDarwin]> {
+    bits<4> func;
+    let Inst{27-4} = 0b000100101111111111110011;
+    let Inst{3-0}   = func;
+  }
+
   // ARMv4T
   // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
   def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=126915&r1=126914&r2=126915&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Wed Mar  2 19:41:01 2011
@@ -809,8 +809,10 @@
   if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR)
     return true;
 
-  // BLXr9 and BX take one GPR reg.
-  if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) {
+  // BLX and BX take one GPR reg.
+  if (Opcode == ARM::BLXr9 || Opcode == ARM::BLXr9_pred ||
+      Opcode == ARM::BLX || Opcode == ARM::BLX_pred ||
+      Opcode == ARM::BX) {
     assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
            "Reg operand expected");
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=126915&r1=126914&r2=126915&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Wed Mar  2 19:41:01 2011
@@ -133,3 +133,6 @@
 
 # CHECK: rsbs r6, r7, r8
 0x08 0x60 0x77 0xe0
+
+# CHECK: blxeq r5
+0x35 0xff 0x2f 0x01

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=126915&r1=126914&r2=126915&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Mar  2 19:41:01 2011
@@ -1632,7 +1632,7 @@
 
     // Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction.
     if (Name == "BL" || Name == "BL_pred" || Name == "BLX" || Name == "BX" ||
-        Name == "TPsoft")
+        Name == "BLX_pred" || Name == "TPsoft")
       return false;
 
     // Ignore VDUPf[d|q] instructions known to conflict with VDUP32[d-q] for