[llvm-commits] [llvm] r126635 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/icmp.ll
Nick Lewycky
nicholas at mxc.ca
Sun Feb 27 22:20:06 PST 2011
Author: nicholas
Date: Mon Feb 28 00:20:05 2011
New Revision: 126635
URL: http://llvm.org/viewvc/llvm-project?rev=126635&view=rev
Log:
The sign of an srem instruction is the sign of its dividend (the first
argument), regardless of the divisor. Teach instcombine about this and fix
test7 in PR9343!
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/trunk/test/Transforms/InstCombine/icmp.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=126635&r1=126634&r2=126635&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Mon Feb 28 00:20:05 2011
@@ -1340,6 +1340,16 @@
}
}
break;
+
+ case Instruction::SRem: {
+ bool TrueIfSigned;
+ if (LHSI->hasOneUse() &&
+ isSignBitCheck(ICI.getPredicate(), RHS, TrueIfSigned)) {
+ // srem has the same sign as its dividend so the divisor is irrelevant.
+ return new ICmpInst(ICI.getPredicate(), LHSI->getOperand(0), RHS);
+ }
+ break;
+ }
}
// Simplify icmp_eq and icmp_ne instructions with integer constant RHS.
@@ -1855,11 +1865,11 @@
return new ICmpInst(ICmpInst::ICMP_SLT, Op0,
ConstantInt::get(CI->getContext(), CI->getValue()+1));
case ICmpInst::ICMP_UGE:
- assert(!CI->isMinValue(false)); // A >=u MIN -> TRUE
+ assert(!CI->isMinValue(false)); // A >=u MIN -> TRUE
return new ICmpInst(ICmpInst::ICMP_UGT, Op0,
ConstantInt::get(CI->getContext(), CI->getValue()-1));
case ICmpInst::ICMP_SGE:
- assert(!CI->isMinValue(true)); // A >=s MIN -> TRUE
+ assert(!CI->isMinValue(true)); // A >=s MIN -> TRUE
return new ICmpInst(ICmpInst::ICMP_SGT, Op0,
ConstantInt::get(CI->getContext(), CI->getValue()-1));
}
@@ -1913,7 +1923,7 @@
ConstantInt::get(I.getContext(), Op1Min));
// Based on the range information we know about the LHS, see if we can
- // simplify this comparison. For example, (x&4) < 8 is always true.
+ // simplify this comparison. For example, (x&4) < 8 is always true.
switch (I.getPredicate()) {
default: llvm_unreachable("Unknown icmp opcode!");
case ICmpInst::ICMP_EQ: {
Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=126635&r1=126634&r2=126635&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Mon Feb 28 00:20:05 2011
@@ -377,3 +377,13 @@
%c = icmp ugt i32 %lhs, %rhs
ret i1 %c
}
+
+; PR9343 #7
+; CHECK: @test39
+; CHECK: ret i1 false
+define i1 @test39(i31 %X, i32 %Y) {
+ %A = zext i31 %X to i32
+ %B = srem i32 %A, %Y
+ %C = icmp slt i32 %B, 0
+ ret i1 %C
+}
More information about the llvm-commits
mailing list