[llvm-commits] [llvm] r126302 - in /llvm/trunk: lib/MC/MCDisassembler/EDOperand.cpp test/MC/Disassembler/X86/enhanced.txt

[Sean Callanan]

Author: spyffe
Date: Tue Feb 22 21:31:28 2011
New Revision: 126302

URL: http://llvm.org/viewvc/llvm-project?rev=126302&view=rev
Log:
Fixed a bug in the enhanced disassembler that caused
it to ignore valid uses of FS and GS as additional
base registers in address computations.  Added a test
case for this.

Modified:
    llvm/trunk/lib/MC/MCDisassembler/EDOperand.cpp
    llvm/trunk/test/MC/Disassembler/X86/enhanced.txt

Modified: llvm/trunk/lib/MC/MCDisassembler/EDOperand.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDOperand.cpp?rev=126302&r1=126301&r2=126302&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDOperand.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDOperand.cpp Tue Feb 22 21:31:28 2011
@@ -152,10 +152,23 @@
       uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
       unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
       int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
-      //unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
-      
+    
       uint64_t addr = 0;
         
+      unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
+        
+      if (segmentReg != 0 && Disassembler.Key.Arch == Triple::x86_64) {
+        unsigned fsID = Disassembler.registerIDWithName("FS");
+        unsigned gsID = Disassembler.registerIDWithName("GS");
+        
+        if (segmentReg == fsID ||
+            segmentReg == gsID) {
+          uint64_t segmentBase;
+          if (!callback(&segmentBase, segmentReg, arg))
+            addr += segmentBase;        
+        }
+      }
+        
       if (baseReg) {
         uint64_t baseVal;
         if (callback(&baseVal, baseReg, arg))
@@ -175,7 +188,7 @@
       result = addr;
       return 0;
     }
-    }
+    } // switch (operandType)
     break;
   case Triple::arm:
   case Triple::thumb:
@@ -203,6 +216,7 @@
       return 0;
     }
     }
+    break;
   }
   
   return -1;

Modified: llvm/trunk/test/MC/Disassembler/X86/enhanced.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/enhanced.txt?rev=126302&r1=126301&r2=126302&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/enhanced.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/enhanced.txt Tue Feb 22 21:31:28 2011
@@ -2,3 +2,5 @@
 
 # CHECK: [o:jne][w:	][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606
 0x0f 0x85 0xf6 0xff 0xff 0xff
+# CHECK: [o:movq][w:	][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:[GS/63]=8
+0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00