[llvm-commits] [llvm] r125457 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/CellSPU/shift_ops.ll test/CodeGen/MBlaze/shift.ll

[Chris Lattner]

Author: lattner
Date: Sun Feb 13 03:02:52 2011
New Revision: 125457

URL: http://llvm.org/viewvc/llvm-project?rev=125457&view=rev
Log:
fix visitShift to properly zero extend the shift amount if the provided operand
is narrower than the shift register.  Doing an anyext provides undefined bits in
the top part of the register.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll
    llvm/trunk/test/CodeGen/MBlaze/shift.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=125457&r1=125456&r2=125457&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sun Feb 13 03:02:52 2011
@@ -2424,31 +2424,30 @@
 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
   SDValue Op1 = getValue(I.getOperand(0));
   SDValue Op2 = getValue(I.getOperand(1));
-  if (!I.getType()->isVectorTy() &&
-      Op2.getValueType() != TLI.getShiftAmountTy()) {
+  
+  MVT ShiftTy = TLI.getShiftAmountTy();
+  unsigned ShiftSize = ShiftTy.getSizeInBits();
+  unsigned Op2Size = Op2.getValueType().getSizeInBits();
+  
+  // Coerce the shift amount to the right type if we can.
+  if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
+    DebugLoc DL = getCurDebugLoc();
+    
     // If the operand is smaller than the shift count type, promote it.
-    EVT PTy = TLI.getPointerTy();
-    EVT STy = TLI.getShiftAmountTy();
-    if (STy.bitsGT(Op2.getValueType()))
-      Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
-                        TLI.getShiftAmountTy(), Op2);
+    MVT PtrTy = TLI.getPointerTy();
+    if (ShiftSize > Op2Size)
+      Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
+    
     // If the operand is larger than the shift count type but the shift
     // count type has enough bits to represent any shift value, truncate
     // it now. This is a common case and it exposes the truncate to
     // optimization early.
-    else if (STy.getSizeInBits() >=
-             Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
-      Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
-                        TLI.getShiftAmountTy(), Op2);
-    // Otherwise we'll need to temporarily settle for some other
-    // convenient type; type legalization will make adjustments as
-    // needed.
-    else if (PTy.bitsLT(Op2.getValueType()))
-      Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
-                        TLI.getPointerTy(), Op2);
-    else if (PTy.bitsGT(Op2.getValueType()))
-      Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
-                        TLI.getPointerTy(), Op2);
+    else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
+      Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
+    // Otherwise we'll need to temporarily settle for some other convenient
+    // type.   Type legalization will make adjustments as needed.
+    else
+      Op2 = DAG.getZExtOrTrunc(Op2, DL, PtrTy);
   }
 
   setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),

Modified: llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll?rev=125457&r1=125456&r2=125457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll Sun Feb 13 03:02:52 2011
@@ -4,7 +4,7 @@
 ; RUN: grep {shl	}  %t1.s | count 9
 ; RUN: grep {shli	}  %t1.s | count 3
 ; RUN: grep {xshw	}  %t1.s | count 5
-; RUN: grep {and	}  %t1.s | count 5
+; RUN: grep {and	}  %t1.s | count 14
 ; RUN: grep {andi	}  %t1.s | count 2
 ; RUN: grep {rotmi	}  %t1.s | count 2
 ; RUN: grep {rotqmbyi	}  %t1.s | count 1

Modified: llvm/trunk/test/CodeGen/MBlaze/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MBlaze/shift.ll?rev=125457&r1=125456&r2=125457&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MBlaze/shift.ll (original)
+++ llvm/trunk/test/CodeGen/MBlaze/shift.ll Sun Feb 13 03:02:52 2011
@@ -13,7 +13,6 @@
     ; FUN:        andi
     ; FUN:        add
     ; FUN:        bnei
-    ; SHT-NOT:    andi
     ; SHT-NOT:    bnei
 
     ret i8 %tmp.1
@@ -50,7 +49,6 @@
     ; FUN:        andi
     ; FUN:        add
     ; FUN:        bnei
-    ; SHT-NOT:    andi
     ; SHT-NOT:    bnei
 
     ret i16 %tmp.1