[llvm-commits] Patch review #9165

[Rotem, Nadav]

Hi, This is a fix for #9165.

http://llvm.org/bugs/show_bug.cgi?id=9165


The problem appeared between 2.7 and 2.8 and is still in the LLVM trunk.
After the 2.7 release some code was added in X86ISelLowering:

// For SSE 4.1, use insertps to put the high elements into the low element.
if (getSubtarget()->hasSSE41()) {
...

This optimization created a new pattern, which was previously unexpected.
The pattern was a lowering of the BUILD_VECTOR operation to a sequence of
simple BUILD_VECTOR (all zero or undef) and a sequence of insert-elements.  The
next stage, the DAGCombining, is the last stage before the instruction
selection. This phase found the new pattern and created a complex BUILD_VECTOR,
which was illegal. The last-phase dag-combining is only allowed to create legal
instructions. In my patch I added a check that the new pattern is only
optimized if we are in the LegalOperations mode, which is allowed to crate
illegal instructions such as the one we encountered.

Patch:

Index: DAGCombiner.cpp
===================================================================
--- DAGCombiner.cpp     (revision 124985)
+++ DAGCombiner.cpp     (working copy)
@@ -6377,7 +6377,8 @@

   // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
   // vector with the inserted element.
-  if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
+  if (!LegalOperations && InVec.getOpcode() == ISD::BUILD_VECTOR &&
+      isa<ConstantSDNode>(EltNo)) {
     unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
     SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
                                 InVec.getNode()->op_end());

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