[llvm-commits] [llvm] r123927 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/arm_instructions.s
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Thu Jan 20 10:06:58 PST 2011
Author: bruno
Date: Thu Jan 20 12:06:58 2011
New Revision: 123927
URL: http://llvm.org/viewvc/llvm-project?rev=123927&view=rev
Log:
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/arm_instructions.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123927&r1=123926&r2=123927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jan 20 12:06:58 2011
@@ -3555,19 +3555,45 @@
// Coprocessor Instructions. For disassembly only.
//
-def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
- nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
- NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
- [/* For disassembly only; pattern left blank */]> {
- let Inst{4} = 0;
+def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
+ c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
+ NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
+ [/* For disassembly only; pattern left blank */]> {
+ bits<4> opc1;
+ bits<4> CRn;
+ bits<4> CRd;
+ bits<4> cop;
+ bits<3> opc2;
+ bits<4> CRm;
+
+ let Inst{3-0} = CRm;
+ let Inst{4} = 0;
+ let Inst{7-5} = opc2;
+ let Inst{11-8} = cop;
+ let Inst{15-12} = CRd;
+ let Inst{19-16} = CRn;
+ let Inst{23-20} = opc1;
}
-def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
- nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
- NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
+def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
+ c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
+ NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111;
- let Inst{4} = 0;
+ bits<4> opc1;
+ bits<4> CRn;
+ bits<4> CRd;
+ bits<4> cop;
+ bits<3> opc2;
+ bits<4> CRm;
+
+ let Inst{3-0} = CRm;
+ let Inst{4} = 0;
+ let Inst{7-5} = opc2;
+ let Inst{11-8} = cop;
+ let Inst{15-12} = CRd;
+ let Inst{19-16} = CRn;
+ let Inst{23-20} = opc1;
}
class ACI<dag oops, dag iops, string opc, string asm>
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123927&r1=123926&r2=123927&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jan 20 12:06:58 2011
@@ -53,11 +53,11 @@
bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
int TryParseRegister();
- bool TryParseMCRName(SmallVectorImpl<MCParsedAsmOperand*>&);
+ bool TryParseCoprocessorOperandName(SmallVectorImpl<MCParsedAsmOperand*>&);
bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
- bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, bool isMCR);
+ bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, bool hasCoprocOp);
bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
MCSymbolRefExpr::VariantKind Variant);
@@ -602,7 +602,7 @@
return false;
}
-static int MatchMCRName(StringRef Name) {
+static int MatchCoprocessorOperandName(StringRef Name) {
// Use the same layout as the tablegen'erated register name matcher. Ugly,
// but efficient.
switch (Name.size()) {
@@ -643,17 +643,18 @@
return -1;
}
-/// TryParseMCRName - Try to parse an MCR/MRC symbolic operand
-/// name. The token must be an Identifier when called, and if it is a MCR
-/// operand name, the token is eaten and the operand is added to the
-/// operand list.
+/// TryParseCoprocessorOperandName - Try to parse an coprocessor related
+/// instruction with a symbolic operand name. The token must be an Identifier
+/// when called, and if it is a coprocessor related operand name, the token is
+/// eaten and the operand is added to the operand list. Example: operands like
+/// "p1", "p7", "c3", "c5", ...
bool ARMAsmParser::
-TryParseMCRName(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+TryParseCoprocessorOperandName(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
- int Num = MatchMCRName(Tok.getString());
+ int Num = MatchCoprocessorOperandName(Tok.getString());
if (Num == -1)
return true;
@@ -966,7 +967,7 @@
/// Parse a arm instruction operand. For now this parses the operand regardless
/// of the mnemonic.
bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- bool isMCR){
+ bool hasCoprocOp){
SMLoc S, E;
switch (getLexer().getKind()) {
default:
@@ -975,7 +976,7 @@
case AsmToken::Identifier:
if (!TryParseRegisterWithWriteBack(Operands))
return false;
- if (isMCR && !TryParseMCRName(Operands))
+ if (hasCoprocOp && !TryParseCoprocessorOperandName(Operands))
return false;
// Fall though for the Identifier case that is not a register or a
@@ -1264,15 +1265,22 @@
Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
}
- bool isMCR = (Head == "mcr" || Head == "mcr2" ||
- Head == "mcrr" || Head == "mcrr2" ||
- Head == "mrc" || Head == "mrc2" ||
- Head == "mrrc" || Head == "mrrc2");
+ // Enable the parsing of instructions containing coprocessor related
+ // asm syntax, such as coprocessor names "p7, p15, ..." and coprocessor
+ // registers "c1, c3, ..."
+ // FIXME: we probably want AsmOperandClass and ParserMatchClass declarations
+ // in the .td file rather than hacking the ASMParser for every symbolic
+ // operand type.
+ bool hasCoprocOp = (Head == "mcr" || Head == "mcr2" ||
+ Head == "mcrr" || Head == "mcrr2" ||
+ Head == "mrc" || Head == "mrc2" ||
+ Head == "mrrc" || Head == "mrrc2" ||
+ Head == "cdp" || Head == "cdp2");
// Read the remaining operands.
if (getLexer().isNot(AsmToken::EndOfStatement)) {
// Read the first operand.
- if (ParseOperand(Operands, isMCR)) {
+ if (ParseOperand(Operands, hasCoprocOp)) {
Parser.EatToEndOfStatement();
return true;
}
@@ -1281,7 +1289,7 @@
Parser.Lex(); // Eat the comma.
// Parse and remember the operand.
- if (ParseOperand(Operands, isMCR)) {
+ if (ParseOperand(Operands, hasCoprocOp)) {
Parser.EatToEndOfStatement();
return true;
}
Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=123927&r1=123926&r2=123927&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Thu Jan 20 12:06:58 2011
@@ -154,3 +154,8 @@
@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
mrrc2 p7, #1, r5, r4, c1
+@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
+ cdp p7, #1, c1, c1, c1, #4
+@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
+ cdp2 p7, #1, c1, c1, c1, #4
+
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