[llvm-commits] [llvm] r123892 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Andrew Trick
atrick at apple.com
Wed Jan 19 22:21:59 PST 2011
Author: atrick
Date: Thu Jan 20 00:21:59 2011
New Revision: 123892
URL: http://llvm.org/viewvc/llvm-project?rev=123892&view=rev
Log:
Selection DAG scheduler register pressure heuristic fixes.
Added a check for already live regs before claiming HighRegPressure.
Fixed a few cases of checking the wrong number of successors.
Added some tracing until these heuristics are better understood.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=123892&r1=123891&r2=123892&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Thu Jan 20 00:21:59 2011
@@ -1589,6 +1589,8 @@
CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers);
}
+// Lower priority means schedule further down. For bottom-up scheduling, lower
+// priority SUs are scheduled before higher priority SUs.
unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
assert(SU->NodeNum < SethiUllmanNumbers.size());
unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
@@ -1641,6 +1643,14 @@
if (I->isCtrl())
continue;
SUnit *PredSU = I->getSUnit();
+ // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
+ // counts data deps. To be more precise, we could maintain a
+ // NumDataSuccsLeft count.
+ if (PredSU->NumSuccsLeft != PredSU->Succs.size()) {
+ DEBUG(dbgs() << " SU(" << PredSU->NodeNum << ") live across SU("
+ << SU->NodeNum << ")\n");
+ continue;
+ }
const SDNode *PN = PredSU->getNode();
if (!PN->isMachineOpcode()) {
if (PN->getOpcode() == ISD::CopyFromReg) {
@@ -1735,7 +1745,9 @@
if (I->isCtrl())
continue;
SUnit *PredSU = I->getSUnit();
- if (PredSU->NumSuccsLeft != PredSU->NumSuccs)
+ // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
+ // counts data deps.
+ if (PredSU->NumSuccsLeft != PredSU->Succs.size())
continue;
const SDNode *PN = PredSU->getNode();
if (!PN->isMachineOpcode()) {
@@ -1814,7 +1826,9 @@
if (I->isCtrl())
continue;
SUnit *PredSU = I->getSUnit();
- if (PredSU->NumSuccsLeft != PredSU->NumSuccs)
+ // NumSuccsLeft counts all deps. Don't compare it with NumSuccs which only
+ // counts data deps.
+ if (PredSU->NumSuccsLeft != PredSU->Succs.size())
continue;
const SDNode *PN = PredSU->getNode();
if (!PN->isMachineOpcode()) {
@@ -2003,12 +2017,11 @@
int LDepth = (int)left->getDepth();
int RDepth = (int)right->getDepth();
- DEBUG(dbgs() << " Comparing latency of SU #" << left->NodeNum
- << " depth " << LDepth << " vs SU #" << right->NodeNum
- << " depth " << RDepth << "\n");
-
if (EnableSchedCycles) {
if (LDepth != RDepth)
+ DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
+ << ") depth " << LDepth << " vs SU (" << right->NodeNum
+ << ") depth " << RDepth << ")\n");
return LDepth < RDepth ? 1 : -1;
}
else {
@@ -2119,10 +2132,16 @@
bool RHigh = SPQ->HighRegPressure(right);
// Avoid causing spills. If register pressure is high, schedule for
// register pressure reduction.
- if (LHigh && !RHigh)
+ if (LHigh && !RHigh) {
+ DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
+ << right->NodeNum << ")\n");
return true;
- else if (!LHigh && RHigh)
+ }
+ else if (!LHigh && RHigh) {
+ DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
+ << left->NodeNum << ")\n");
return false;
+ }
else if (!LHigh && !RHigh) {
int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
if (result != 0)
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